AT90S1200-4YC Atmel, AT90S1200-4YC Datasheet - Page 15

• Manufacturer Part Number: AT90S1200-4YC
• Description: IC MCU 1K FLSH 4MHZ LV 20SSOP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S1200-4YC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: POR, WDT
• Number Of I /o: 15
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Ram Size: -
• Data Converters: -

Interrupt Handling
General Interrupt Mask
Register
0838H–AVR–03/02
–
GIMSK
Figure 17. Watchdog Reset during Operation
The AT90S1200 has two Interrupt Mask Control Registers: the GIMSK (General Inter-
rupt Mask Register) at I/O space address $3B and the TIMSK (Timer/Counter Interrupt
Mask Register) at I/O address $39.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-
bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag
bit position(s) to be cleared.
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag, and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S1200 and always reads as zero.
Bit
$3B
Read/Write
Initial Value
R
7
0
-
INT0
R/W
6
0
R
5
0
-
R
4
0
-
R
3
0
-
R
2
0
-
AT90S1200
R
1
0
-
R
0
0
-
GIMSK
15