AT91M43300-25CI Atmel, AT91M43300-25CI Datasheet - Page 7

• Manufacturer Part Number: AT91M43300-25CI
• Description: IC ARM7 MCU 144 BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M43300-25CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: WDT
• Number Of I /o: 58
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

5. Architectural Overview
5.1
1322B–ATARM–12-Dec-05
PDC: Peripheral Data Controller
The AT91M43300 architecture consists of two main buses, the Advanced System Bus (ASB)
and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It
interfaces the processor with the on-chip 32-bit memories and the external memories and
devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-
chip peripherals and is optimized for low power consumption. The AMBA Bridge provides an
interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI
and the on and off-chip memories without processor intervention. Most importantly, the PDC
removes the processor interrupt handling overhead and significantly reduces the number of
clock cycles required for a data transfer. It can transfer up to 64k contiguous bytes without repro-
gramming the starting address. As a result, the performance of the microcontroller is increased
and the power consumption reduced.
The AT91M43300 peripherals are designed to be easily programmable with a minimum number
of instructions. Each peripheral has a 16K byte address space allocated in the upper 3M bytes of
the 4G byte address space. Except for the interrupt controller, the peripheral base address is the
lowest address of its memory space. The peripheral register set is composed of control, mode,
data, status and interrupt registers.
To maximize the efficiency of bit manipulation, frequently written registers are mapped into three
memory locations. The first address is used to set the individual register bits, the second resets
the bits and the third address reads the value stored in the register. A bit can be set or reset by
writing a one to the corresponding position at the appropriate address. Writing a zero has no
effect. Individual bits can thus be modified without having to use costly read-modify-write and
complex bit manipulation instructions.
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O con-
troller. The PIO controller can be programmed to insert an input filter on each pin or generate an
interrupt on a signal change. After reset, the user must carefully program the PIO Controller in
order to define which peripheral signals are connected with off-chip logic.
The ARM7TDMI processor operates in little-endian mode in the AT91M43300 microcontroller.
The processor’s internal architecture and the ARM and Thumb instruction sets are described in
the ARM7TDMI Datasheet. The memory map and the on-chip peripherals are described in the
datasheet entitled “AT91M63200 Datasheet” (Literature No. 1028). Electrical characteristics for
the AT91M43300 are documented in the “AT91M63200 Electrical and Mechanical Characteris-
tics” (Literature No. 1090).
The ARM Standard In-Circuit-Emulation debug interface is supported via the ICE port of the
AT91M43300 via the JTAG/ICE port when JTAGSEL is low. IEEE JTAG boundary scan is sup-
ported via the JTAG/ICE port when JTAGSEL is high.
The AT91M43300 has an 8-channel PDC dedicated to the three on-chip USARTs and to the
SPI. One PDC channel is connected to the receiving channel and one to the transmitting chan-
nel of each peripheral.
The user interface of a PDC channel is integrated in the memory space of each USART channel
and in the memory space of the SPI. It contains a 32-bit address pointer register and a 16-bit
count register. When the programmed data is transferred, an end of transfer interrupt is gener-
AT91M43300
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