PIC17C756A/CL Microchip Technology, PIC17C756A/CL Datasheet - Page 133
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756A/CL
Manufacturer Part Number
PIC17C756A/CL
Description
IC MCU EPROM 16KX16 A/D 68CLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A/CL
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
EPROM
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-CLCC Window, 68-CERQUAD
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 133 of 304
- Download datasheet (6Mb)
15.0
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit
Figure 15-1 shows a block diagram for the SPI mode,
while Figure 15-2 and Figure 15-3 show the block
diagrams for the two different I
FIGURE 15-1:
2000 Microchip Technology Inc.
SDO
SCK
SDI
SS
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
Read
SS Control
SMP:CKE
Select
Edge
Enable
bit0
Select
Edge
SSPBUF reg
SPI MODE BLOCK
DIAGRAM
Data to TX/RX in SSPSR
Data Direction bit
2
SSPSR reg
TM
SSPM3:SSPM0
Clock Select
(I
4
2
C)
2
C modes of operation.
2
Write
Prescaler
4, 16, 64
Clock
Shift
TMR2 Output
Data Bus
Internal
2
Tosc
FIGURE 15-2:
FIGURE 15-3:
SDA
SCL
SDA
SCL
Baud Rate Generator
SSPADD<6:0>
7
Read
Read
Clock
Clock
Shift
Shift
START and STOP bit
MSb
MSb
Detect/Generate
STOP bit Detect
I
DIAGRAM
I
BLOCK DIAGRAM
2
Match Detect
2
SSPADD reg
SSPADD reg
SSPBUF reg
SSPBUF reg
Match detect
START and
SSPSR reg
SSPSR reg
PIC17C7XX
C SLAVE MODE BLOCK
C MASTER MODE
LSb
LSb
DS30289B-page 133
Write
Write
(SSPSTAT reg)
(SSPSTAT reg)
Clear/Set P, bit
and Set SSPIF
Set/Clear S bit
Data Bus
Data Bus
Internal
Internal
Call Detected
Call Detected
Set, Reset
S, P bits
Addr Match
Addr Match
or General
or General
and
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