PIC17C42A/JW Microchip Technology, PIC17C42A/JW Datasheet - Page 86
![IC MCU EPROM 2KX16 PWM 40CDIP](/photos/6/63/66338/150-40-cdip_sml.jpg)
PIC17C42A/JW
Manufacturer Part Number
PIC17C42A/JW
Description
IC MCU EPROM 2KX16 PWM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C42A-16P.pdf
(241 pages)
3.PIC17C42A-16P.pdf
(4 pages)
Specifications of PIC17C42A/JW
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
4KB (2K x 16)
Program Memory Type
EPROM, UV
Ram Size
232 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
For Use With
DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C42A/JW
Manufacturer:
MICROCHIP
Quantity:
10
Company:
Part Number:
PIC17C42A/JW
Manufacturer:
EON
Quantity:
32 000
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PIC17C4X
13.1
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. Table 13-1 shows
the formula for computation of the baud rate for differ-
ent USART modes. These only apply when the USART
is in synchronous master mode (internal clock) and
asynchronous mode.
Given the desired baud rate and Fosc, the nearest inte-
ger value between 0 and 255 can be calculated using
the formula below. The error in baud rate can then be
determined.
TABLE 13-1:
X = value in SPBRG (0 to 255)
TABLE 13-2:
DS30412C-page 86
Address
13h, Bank 0
15h, Bank 0
17h, Bank 0
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used by the Baud Rate Generator.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
SYNC
0
1
USART Baud Rate Generator (BRG)
Asynchronous
Synchronous
Name
RCSTA
TXSTA
SPBRG
Mode
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Baud rate generator register
CSRC
SPEN
Bit 7
F
F
Bit 6
RX9
TX9
OSC
OSC
Baud Rate
/(64(X+1))
/(4(X+1))
SREN
TXEN
Bit 5
CREN
SYNC
Bit 4
Bit 3
—
—
Example 13-1 shows the calculation of the baud rate
error for the following conditions:
EXAMPLE 13-1: CALCULATING BAUD
Writing a new value to the SPBRG, causes the BRG
timer to be reset (or cleared), this ensures that the BRG
does not wait for a timer overflow before outputting the
new baud rate.
Desired Baud rate=Fosc / (64 (X + 1))
Error =
FERR
Bit 2
—
F
Desired Baud Rate = 9600
SYNC = 0
9600 =
X
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
=
OSC
OERR
TRMT
Bit 1
= 16 MHz
=
9615
(Calculated Baud Rate - Desired Baud Rate)
(9615 - 9600) / 9600
0.16%
16000000 /(64 (X + 1))
25.042 = 25
RATE ERROR
Desired Baud Rate
RX9D
TX9D
Bit 0
1996 Microchip Technology Inc.
0000 -00x
0000 --1x
xxxx xxxx
Power-on
Value on
Reset
other resets
Value on all
0000 -00u
0000 --1u
uuuu uuuu
(Note1)
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