PIC16C63/JW Microchip Technology, PIC16C63/JW Datasheet

IC MCU EPROM 4KX14 PWM 28CDIP

PIC16C63/JW

Manufacturer Part Number
PIC16C63/JW
Description
IC MCU EPROM 4KX14 PWM 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr

Specifications of PIC16C63/JW

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
For Use With
DVMCPA - KIT DVR BOARD EVAL SYSTEM MXDEV1
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
The PIC16C63 (Rev. A) parts you have received con-
form
(DS30234D), except for the anomalies described
below.
All the problems listed here will be addressed in future
revisions of the PIC16C63 silicon.
1. Module: CCP (Compare Mode)
TABLE 1:
 2001 Microchip Technology Inc.
CCPxM<3:0> =
CCP Mode
The Compare mode may not operate as expected
when configuring the compare match to drive the
I/O pin low (CCPxM<3:0> = 1001).
When the CCP module is changed to compare
output low (CCPxM<3:0> = 1001) from any other
non-compare CCP mode, the I/O pin will immedi-
ately be driven low, regardless of the state of the
I/O data latch. The pin will remain low when the
compare match occurs (see Table 1).
However, when the CCP module is changed to
compare output high (CCPxM<3:0> = 1000) from
any other CCP mode, the I/O pin will immediately
be driven low, regardless of the state of the I/O
data latch. The pin will be driven high when the
compare match occurs.
functionally
0xxx
1000
1001
101x
11xx
COMPARE OUTPUT LOW
SWITCHING
to
PIC16C63 Rev. A Silicon Errata Sheet
I/O pin
State
H
H
H
H
H
L
L
L
L
L
the
Device
1001
Change CCP to
CCPxM<3:0> =
H
L
L
L
L
L
L
L
Data
1000
Sheet
L
L
L
L
L
L
L
L
2. Module: CCP (Compare Mode)
3. Module: SSP Module (I
Work around
To have the I/O pin high until the compare match
low occurs, force a compare match high to get the
I/O pin into the high state, then reconfigure the
compare match to force the I/O low when the com-
pare condition occurs.
The special event trigger of the Compare mode
may not occur if both of the following conditions
exist:
CCP1
CCP2
The interrupt for the compare event will still be
generated, but no special event trigger will occur.
Work around
Use the Interrupt Service Routine instead of using
the special event trigger to reset Timer1 (and start
an A/D conversion, if applicable).
If the bus is active when the I
and the next 8-bits of data on the bus match the
address of the device, then the SSP module will
generate an Acknowledge pulse.
Work around
Before enabling the I
is not active.
Unit
An instruction, one cycle (T
Timer1/Compare register match has literal
data equal to the address of a CCP register
being used. Specific cases include:
An instruction in the same cycle as a
Timer1/Compare register match has an
MSb of ‘0’.
PIC16C63
CCP1CON
CCP2C0N
Register
CCPR1H
CCPR2H
CCPR1L
CCPR2L
2
C mode, ensure that the bus
2
C™ mode)
2
C mode is enabled,
CY
) prior to a
DS80094A-page 1
Literal Data
1Ch
1Dh
15h
16h
17h
1Bh

Related parts for PIC16C63/JW

PIC16C63/JW Summary of contents

Page 1

... 11xx L L  2001 Microchip Technology Inc. PIC16C63 Work around Data Sheet To have the I/O pin high until the compare match low occurs, force a compare match high to get the I/O pin into the high state, then reconfigure the compare match to force the I/O low when the com- pare condition occurs ...

Page 2

... TMR1H:TMR1L = 00:00 (TMR1IF is not set.) Work around To preserve Timer1 register values: a) Read Timer1 register values into “shadow” registers. b) Perform any write instruction(s) on the shadow registers. c) Write the shadow register values back into the Timer1 registers.  2001 Microchip Technology Inc. ...

Page 3

... When the USART (SCI) is configured in Asynchro- nous mode with the BRGH bit set, a high number of receive errors may be experienced. For asyn- chronous receive operations recommended that the USART be configured with the BRGH bit cleared.  2001 Microchip Technology Inc. PIC16C63 DS80094A-page 3 ...

Page 4

... Single Byte 40 — — 1. Continuous — — (1) Single Byte 40 — — 1 — — ( Data Sheet Specification Units Min Typ Max — — Data Sheet Specification Units Min Typ Max — — N. — — N. N.A.  2001 Microchip Technology Inc. ...

Page 5

... Clock (Input to Prescaler) Write to TMR1H and/or TMR1L Register(s) TMR1H:TMR1L Increments  2001 Microchip Technology Inc. PIC16C63 When the TMR1H and/or TMR1L registers are written while this clock is low, TMR1 will not incre- ment on the next rising edge of this clock, but must first have a falling clock and the rising clock for TMR1 to increment ...

Page 6

... Data Sheet Specification Units Min Typ Max 3.70 — 4.30 V  2001 Microchip Technology Inc. ...

Page 7

... L , SEEVAL, MPLAB and The EE OQ Embedded Control Solutions Company are registered trade- marks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, Filter- Lab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, SelectMode and microPort are trademarks of Microchip Technology Incorporated in the U ...

Page 8

... Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec- tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. ...

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