PIC16C74/JW Microchip Technology, PIC16C74/JW Datasheet - Page 38
![MICRO CTRL 4K 20MHZ EPROM 40CDIP](/photos/6/63/66338/150-40-cdip_sml.jpg)
PIC16C74/JW
Manufacturer Part Number
PIC16C74/JW
Description
MICRO CTRL 4K 20MHZ EPROM 40CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C72-04SO.pdf
(289 pages)
Specifications of PIC16C74/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-CDIP (0.600", 15.24mm) Window
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C74/JW
Manufacturer:
Microchip
Quantity:
29
- Current page: 38 of 289
- Download datasheet (3Mb)
PIC16C7X
4.2.2.7
This register contains the CCP2 interrupt flag bit.
FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh)
DS30390E-page 38
bit7
bit 7-1: Unimplemented: Read as '0'
bit 0:
U-0
—
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
PIR2 REGISTER
Applicable Devices
72 73 73A 74 74A 76 77
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
.
Note:
U-0
—
CCP2IF
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
1997 Microchip Technology Inc.
read as ‘0’
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