DS2251T-128-16# Maxim Integrated Products, DS2251T-128-16# Datasheet - Page 5

• Manufacturer Part Number: DS2251T-128-16#
• Description: IC MCU 128KB 16MHZ 72-SIMM
• Manufacturer: Maxim Integrated Products
• Series: DS225xr

Specifications of DS2251T-128-16#

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: SRAM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 72-SIMM
• Processor Series: DS2251T
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 128 KB
• Data Ram Size: 128 KB
• Interface Type: UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19, 18
54–41
63–56
PIN
15
16
17
29
30
20
40
72
64
66
67
31
9
P3.5/T1. General-purpose I/O port pin 3.5. Also serves as the Timer 1 input.
P3.6/
operation.
P3.7/
operation.
RST. Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin
is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit
is not needed and is NOT recommended.
memory when using the Expanded bus. It is normally an output and should be unconnected
if not used.
ALE. Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data
bus on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent
latch.
XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is
the input to an inverting amplifier and XTAL2 is the output.
GND. Logic ground.
V
BA15. Monitor test point to reflect the logical value of A15. Not needed for memory access.
BA13–BA 0. Byte-wide Address bus bits 13–0. This bus is combined with the non-
multiplexed data bus (BD7–BD0) to access onboard NV SRAM and off-board peripherals.
Peripheral decoding is performed using
BA14 or BA15 are not needed. Read/write access is controlled by R/
directly to memory-mapped peripherals.
BD7–BD0. Byte-wide Data Bus Bits 7–0. This 8-bit bi-directional bus is combined with the
non-multiplexed address bus (BA14–BA0) to access on-board NV SRAM and off-board
peripherals.
R/
bus. It is controlled by the memory map and Partition. The blocks selected as Program
(ROM) will be write-protected. This signal is also used for the write enable to off-board
peripherals.
when the PES bit is set to a logic 1.
type of peripheral function.
when the PES bit is set to a logic 1.
type of peripheral function.
that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading
on power-up. This signal is pulled up internally.
PSEN
PE3
PE4
PROG
CC
W
. +5V
. Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh
. Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh
. Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide
WR
RD
. Program Store Enable. This active low signal is used to enable an external program
. Invokes the Bootstrap loader on a falling edge. This signal should be debounced so
. General-purpose I/O port pin. Also serves as the read strobe for Expanded bus
. General-purpose I/O port pin. Also serves as the write strobe for Expanded bus
PE3
PE4
5 of 22
DESCRIPTION
PE3
is not lithium backed and can be connected to any
is not lithium backed and can be connected to any
and
PE4
. These are on 16k boundaries, so
W
. BA13–BA0 connect