DS80C390-QNR Maxim Integrated Products, DS80C390-QNR Datasheet - Page 3

• Manufacturer Part Number: DS80C390-QNR
• Description: IC MPU CAN DUAL HS IND 68-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 80Cr

Specifications of DS80C390-QNR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.85 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-LCC, 68-PLCC
• Processor Series: DS80C390
• Core: 8051
• Data Bus Width: 8 bit
• Program Memory Size: 4 KB
• Data Ram Size: 4 KB
• Interface Type: CAN, IrDA
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 3.85 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
Note 11:
Oscillator Frequency
ALE Pulse Width
Port 0 Instruction Address or CE0–4
Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Port 0 Address to Valid Instruction In
Port 2, 4 Address to Valid Instruction
In
PSEN Low to Address Float
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value t
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value
Timing table. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD, and WR with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.
PARAMETER
SYMBOL
1 / t
t
t
t
t
t
t
t
t
LLAX1
t
t
t
t
AVIV1
AVIV2
PLPH
LHLL
AVLL
PLAZ
LLPL
PXIX
PXIZ
LLIV
PLIV
CLCL
External oscillator
External crystal
CONDITIONS
3 of 53
MIN
0
1
0
40MHz
MAX
40
40
0
0.125 t
0.125 t
0.125 t
0.5 t
0.375 t
MIN
VARIABLE CLOCK
- 5
0
MCS
1
0
MCS
MCS
MCS
MCS
- 8
- 5
- 5
- 5
0.625 t
0.875 t
0.75 t
0.5 t
0.25 t
MAX
MCS
40
40
MCS
0
MCS
MCS
MCS
MCS
- 20
- 22
- 20
- 5
- 30
is a function
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns