SAK-C164CI-L25M CA+ Infineon Technologies, SAK-C164CI-L25M CA+ Datasheet - Page 57

IC MCU 16BIT FULL FUNC MQFP-80-1

SAK-C164CI-L25M CA+

Manufacturer Part Number
SAK-C164CI-L25M CA+
Description
IC MCU 16BIT FULL FUNC MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAK-C164CI-L25M CA+

Core Processor
C166
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
1xASC, 1xSSC
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
59
Number Of Timers
5
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
25.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
K164CIL25MCAZNT
K164CIL25MCAZXT
SAKC164CIL25MCAT
SP000059303
SP000103496
Direct Drive
When direct drive is configured (CLKCFG = 011
disabled and the CPU clock is directly driven from the internal oscillator with the input
clock signal.
The frequency of
f
f
The timings listed below that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances. This minimum value
can be calculated via the following formula:
For two consecutive TCLs the deviation caused by the duty cycle of
so the duration of 2TCL is always 1/
be used only once for timings that require an odd number of TCLs (1, 3, …). Timings that
require an even number of TCLs (2, 4, …) may use the formula 2TCL = 1/
Data Sheet
CPU
OSC
.
(i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock
TCL
min
= 1/
f
OSC
f
CPU
× DC
directly follows the frequency of
min
(DC = duty cycle)
f
OSC
. The minimum value TCL
53
B
) the on-chip phase locked loop is
f
OSC
so the high and low time of
f
OSC
min
therefore has to
is compensated
C164CL/SL
f
V2.0, 2001-05
OSC
C164CI/SI
.

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