DS89C450-QNG Maxim Integrated Products, DS89C450-QNG Datasheet - Page 36

• Manufacturer Part Number: DS89C450-QNG
• Description: IC MCU FLASH 64KB 25MHZ 44-PLCC
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C450-QNG

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LCC, 44-PLCC
• Processor Series: DS89C450
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: DS89C450-KIT#
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Interrupt Priority
There are five levels of interrupt priority: Level 4 to 0. The highest interrupt priority is level 4, which is reserved for
the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each
interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is
enabled. All interrupts also have a natural hierarchy. In this manner, when a set of interrupts has been assigned the
same priority, a second hierarchy determines which interrupt is allowed to take precedence. The natural hierarchy
is determined by analyzing potential interrupts in a sequential manner with the order listed in
The processor indicates that an interrupt condition occurred by setting the respective flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Unless marked in
cleared by software.
Table 11. Interrupt Summary
Note 1: If the interrupt is edge triggered, the flag is cleared automatically by hardware when the service routine is vectored to. If the interrupt
Note 2: The flag is cleared automatically by hardware when the service routine is vectored to.
Power Fail
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port 0
Timer 2 Overflow
Serial Port 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
Watchdog
INTERRUPT
is level triggered, the flag follows the state of the pin.
VECTOR
0Bh
1Bh
2Bh
3Bh
4Bh
5Bh
33h
03h
13h
23h
43h
53h
63h
NATURAL ORDER
12 (Lowest)
0 (Highest)
10
11
1
2
3
4
5
6
7
9
8
TF0 (TCON.5) (Note 2)
TF1 (TCON.7) (Note 2)
IE0 (TCON.1) (Note 1)
IE1 (TCON.3) (Note 1)
DS89C430/DS89C450 Ultra-High-Speed Flash Microcontrollers
WDIF (WDCON.3)
EXF2 (T2CON.6)
RI_0 (SCON0.0);
RI_1 (SCON1.0);
PFI (WDCON.4)
TI_0 (SCON0.1)
TF2 (T2CON.7);
TI_1 (SCON1.1)
36 of 46
IE3 (EXIF.5)
IE5 (EXIF.7)
IE2 (EXIF.4)
IE4 (EXIF.6)
FLAG
EPFI(WDCON.5)
EWDI (EIE.4)
EX2 (EIE.0)
EX3 (EIE.1)
EX4 (EIE.2)
EX5 (EIE.3)
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES0 (IE.4)
ET2 (IE.5)
ES1 (IE.6)
ENABLE
Table
11, all these flags must be
PRIORITY CONTROL
Table
LPWDI (EIP0.4);
MPWDI (EIP1.4)
LPX2 (EIP0.0);
MPX2 (EIP1.0)
LPX3 (EIP0.1);
MPX3 (EIP1.1)
LPX4 (EIP0.2);
MPX4 (EIP1.2)
LPX5 (EIP0.3);
MPX5 (EIP1.3)
LPS1 (IP0.6);
MPS1 (IP1.6)
LPX0 (IP0.0);
MPX0 (IP1.0)
LPT0 (IP0.1);
MPT0 (IP1.1)
LPX1 (IP0.2);
MPX1 (IP1.2)
LPT1 (IP0.3);
MPT1 (IP1.3)
LPS0 (IP0.4);
MPS0 (IP1.4)
LPT2 (IP0.5);
MPT2 (IP1.5)
11.
N/A