SAB-C161PI-LM CA Infineon Technologies, SAB-C161PI-LM CA Datasheet - Page 70

• Manufacturer Part Number: SAB-C161PI-LM CA
• Description: IC MICROCONTROLLER 16BIT MQFP100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C161PI-LM CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 3 KB
• Interface Type: ASC, I2C, SSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 5
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 4 Channel
• Packages: PG-MQFP-100
• Max Clock Frequency: 20.0 MHz
• Sram (incl. Cache): 3.0 KByte
• A / D Input Lines (incl. Fadc): 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: B161PILMCAXT; SABC161PILMCAXT; SP000014345

Data Sheet
Demultiplexed Bus (Reduced Supply Voltage Range) (continued)
(Operating Conditions apply)
ALE cycle time = 4 TCL + 2
Parameter
Data hold after WR
ALE rising edge after RD,
WR
Address hold after WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to
RdCS, WrCS (with RW-
delay)
ALE falling edge to
RdCS, WrCS (no RW-
delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
1)
1)
3)
2)
3)
3)
Symbol
24
26
28
38
39
41
42
43
46
47
48
49
50
51
53
68
A
+
CC 15 +
CC -12 +
CC 0 +
CC -8 -
CC 9 +
CC 19 +
CC -6 +
CC 38 +
CC 63 +
CC 28 +
SR –
SR –
SR –
SR 0
SR –
SR –
C
+
F
Max. CPU Clock
(100 ns at 20 MHz CPU clock without waitstates)
min.
= 20 MHz
F
F
A
A
68
F
A
C
C
C
F
–
–
–
10 -
47 +
–
–
–
20 +
45 +
–
–
–
–
30 +
5 +
C
max.
+ 2
F
A
C
C
F
A
1 / 2TCL = 1 to 20 MHz
TCL - 10
+
-12 +
0 +
-8 -
–
TCL - 16
+
TCL - 6
+
-6
+
–
–
2TCL - 12
+
3TCL - 12
+
2TCL - 22
+
0
–
–
Variable CPU Clock
F
F
A
A
C
C
C
min.
F
A
F
–
–
–
10 -
3TCL - 28
+
–
–
–
2TCL - 30
+
3TCL - 30
+
–
–
–
–
2TCL - 20
+ 2
TCL - 20
+ 2
C
C
C
max.
A
A
+ 2
A
+
+
F
F
A
&3,
1)
1)
1999-07
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns