AT89C5122D-RDRIM Atmel, AT89C5122D-RDRIM Datasheet - Page 137

• Manufacturer Part Number: AT89C5122D-RDRIM
• Description: IC MCU 80C51 W/SMART CARD 64VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C5122D-RDRIM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SmartCard, SPI, UART/USART, USB
• Peripherals: LED, POR, WDT
• Number Of I /o: 46
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-03 - KIT STARTER FOR MCU AT8XC5122/23
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: AT89C5122DRDRIMTR

Functional Description
Operating Modes
4202F–SCR–07/2008
Figure 83 shows a detailed structure of the SPI module.
Figure 83. SPI Module Block Diagram
The Serial Peripheral Interface can be configured as one of the two modes: Master
mode or Salve mode. The configuration and initialization of the SPI module is made
through one register:
•
Once the SPI is configured, the data exchange is made using:
•
•
•
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO). A Slave Select line (SS) allows
individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 84).
SPI Interrupt Request
The Serial Peripheral Control register (SPCON)
SPCON
The Serial Peripheral Status register (SPSTA)
The Serial Peripheral Data register (SPDAT)
Clock
Divider
IntClk
SPR2
/128
/32
/64
/16
SPEN
/8
/4
Clock
Select
SSDIS
MSTR
AT83R5122, AT8xC5122/23
Receive Data Register
SPIF
CPOL
7
Shift Register
WCOL
Internal Bus
6
CPHA
5
SPI
Control
4
3
SPR1
-
2
Clock
Logic
SPCON
1
SPDAT
MODF
SPR0
0
-
M
S
Pin
Control
Logic
-
-
SPSTA
-
8-bit bus
1-bit signal
MOSI
MISO
SCK
SS
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