UPD78F1146AGK-GAJ-AX Renesas Electronics America, UPD78F1146AGK-GAJ-AX Datasheet - Page 638
UPD78F1146AGK-GAJ-AX
Manufacturer Part Number
UPD78F1146AGK-GAJ-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGK-GAJ-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1146AGK-GAJ-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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20.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
636
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
signal when V
generates an internal reset signal when EXLVI < V
Remark The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to
V
V ±0.1 V). When EXLVI drops lower than V
(EXLVI ≥ V
LVI
(V
DD
LVISEL: Bit 2 of LVIM
< V
raise the power supply from the POC detection voltage or lower, the internal reset signal is
generated when the supply voltage (V
internal reset signal is generated when the supply voltage (V
±0.1 V).
EXLVI
LVI
DD
) or when V
), generates an interrupt signal (INTLVI).
< V
LVI
, and releases internal reset when V
DD
becomes V
CHAPTER 20 LOW-VOLTAGE DETECTOR
User’s Manual U17854EJ9V0UD
LVI
or higher (V
EXLVI
DD
DD
DD
) and detection voltage (V
EXLVI
(EXLVI < V
) and detection voltage (V
) < detection voltage (V
, and releases internal reset when EXLVI ≥ V
DD
≥ V
DD
≥ V
LVI
EXLVI
), generates an interrupt signal (INTLVI).
LVI
) or when EXLVI becomes V
.
DD
LVI
) < detection voltage (V
LVI
= 2.07 V ±0.2 V). After that, the
LVI
). When V
), generates an internal reset
DD
drops lower than
EXLVI
LVI
EXLVI
EXLVI
or higher
= 2.07 V
.
= 1.21
EXLVI
),
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