UPD78F1143AGB-GAH-AX Renesas Electronics America, UPD78F1143AGB-GAH-AX Datasheet - Page 297
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UPD78F1143AGB-GAH-AX
Manufacturer Part Number
UPD78F1143AGB-GAH-AX
Description
MCU 16BIT 78K0R/KX3 64-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1143AGB-GAH-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1143AGB-GAH-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4.4 Setting watchdog timer interval interrupt
generated when 75% of the overflow time is reached.
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
Remarks 1. If the overflow time is set to 2
WDTINT
0
1
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is
short, an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
WDTE register). If ACH is not written to the WDTE register before the overflow time, an internal reset
signal is generated.
2. f
Interval interrupt is used.
Interval interrupt is generated when 75% of overflow time is reached.
<When window open period is 25%>
• Overflow time:
• Window close time:
• Window open time:
IL
Window close time
Window open time
: Internal low-speed oscillation clock frequency
= 3.56 to 3.88 ms
2
0 to 2
2
10
10
/f
/f
IL
IL
Table 8-5. Setting of Watchdog Timer Interval Interrupt
10
(MAX.) = 2
(MIN.) × (1 − 0.25) to 2
/f
IL
(MIN.) × (1 − 0.25) = 0 to 2
10
CHAPTER 8 WATCHDOG TIMER
/264 kHz (MAX.) = 3.88 ms
0 to 3.56 ms
3.56 to 3.88 ms
User’s Manual U17854EJ9V0UD
Use of Watchdog Timer Interval Interrupt
25%
10
/f
IL
10
, the window close time and open time are as follows.
/f
IL
(MAX.) = 2
10
0 to 2.37 ms
2.37 to 3.88 ms
/216 kHz (MIN.) × 0.75 = 0 to 3.56 ms
Setting of Window Open Period
50%
10
/216 kHz (MIN.) × 0.75 to 2
0 to 0.119 ms
0.119 to 3.88 ms
75%
None
0 to 3.88 ms
10
/264 kHz (MAX.)
100%
295
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