SAF-XC878CM-16FFI 3V3 AC Infineon Technologies, SAF-XC878CM-16FFI 3V3 AC Datasheet
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAF-XC878CM-16FFI 3V3 AC
Specifications of SAF-XC878CM-16FFI 3V3 AC
Related parts for SAF-XC878CM-16FFI 3V3 AC
SAF-XC878CM-16FFI 3V3 AC Summary of contents
Page 1
XC87xCLM 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2011- ...
Page 2
... Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
Page 3
XC87xCLM 8-Bit Single-Chip Microcontroller Data Sheet V1.5 2011- ...
Page 4
... Subjects (major changes since last revision) Changes from V1.4 2010-08 to V1.5 2011-03 Page 3 A new variant, SAF-XC874CM-13FVA 5V, has been added in Table 2. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. ...
Page 5
Table of Contents 1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
Power-on Reset and PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.3.4 On-Chip Oscillator Characteristics ...
Page 8
Single-Chip Microcontroller 1 Summary of Features The XC87x has the following features: • High-performance XC800 Core – compatible with standard 8051 processor – two clocks per machine cycle architecture (for memory access without wait state) – two data pointers ...
Page 9
... Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM) – 64 bytes of monitor RAM • Packages: – PG-LQFP-64 – PG-VQFN-48 • Temperature range T A – SAF (- °C) – SAX (-40 to 105 °C) – SAK (-40 to 125 °C) 1) SAK product variant does not support power-down mode. Data Sheet : 2 XC87xCLM Summary of Features 1) V1 ...
Page 10
... Industrial), as shown in Table 2. Table 2 Device Profile Sales Type SAF-XC878-13FFI 5V SAF-XC878M-13FFI 5V SAF-XC878CM-13FFI 5V SAF-XC878-16FFI 5V SAF-XC878M-16FFI 5V SAF-XC878CM-16FFI 5V SAF-XC878-13FFI 3V3 SAF-XC878M-13FFI 3V3 Data Sheet CAN LIN BSL Module Support Yes ...
Page 11
... Table 2 Device Profile (cont’d) Sales Type SAF-XC878CM-13FFI 3V3 SAF-XC878-16FFI 3V3 SAF-XC878M-16FFI 3V3 SAF-XC878CM-16FFI 3V3 SAF-XC878-13FFA 5V SAF-XC878CM-13FFA 5V SAF-XC878LM-13FFA 5V SAF-XC878CLM-13FFA 5V SAF-XC878-16FFA 5V SAF-XC878CM-16FFA 5V SAF-XC878LM-16FFA 5V SAF-XC878CLM-16FFA 5V SAX-XC878-13FFA 5V SAX-XC878CM-13FFA 5V SAX-XC878LM-13FFA 5V SAX-XC878CLM-13FFA 5V SAX-XC878-16FFA 5V SAX-XC878CM-16FFA 5V SAX-XC878LM-16FFA 5V SAX-XC878CLM-16FFA 5V SAK-XC878-13FFA 5V SAK-XC878CM-13FFA 5V SAK-XC878LM-13FFA 5V SAK-XC878CLM-13FFA 5V SAK-XC878-16FFA 5V SAK-XC878CM-16FFA 5V SAK-XC878LM-16FFA 5V SAK-XC878CLM-16FFA 5V SAF-XC874LM-16FVA 5V Data Sheet ...
Page 12
... Table 2 Device Profile (cont’d) Sales Type SAF-XC874CM-16FVA 5V SAF-XC874CM-13FVA 5V SAK-XC874LM-16FVA 5V SAK-XC874CM-16FVA 5V SAK-XC874-16FVA 5V SAK-XC874LM-13FVA 5V SAK-XC874CM-13FVA 5V SAK-XC874-13FVA 5V As this document refers to all the derivatives, some description may not apply to a specific product. For simplicity, all versions are referred to by the term XC87x throughout this document ...
Page 13
General Device Information Chapter 2 contains the block diagram, pin configurations, definitions and functions of the XC87x. 2.1 Block Diagram The block diagram of the XC87x is shown in XC87x 8-Kbyte 1) Boot ROM 256-byte RAM + TMS 64-byte ...
Page 14
Logic Symbol The logic symbols of the XC878 and XC874 are shown DDP SSP V AREF V AGND RESET MBC XC878 TMS TM XTAL1 XTAL2 V V DDC SSC Figure 3 XC878 and XC874 Logic Symbol ...
Page 15
Pin Configuration The pin configuration of the XC878, which is based on the PG-LQFP-64, is shown in Figure 4, while that of the XC874, which is based on the PG-VQFN-48 package, is shown in Figure ...
Page 16
P3.4 38 P3.5 39 RESET 40 V SSP 41 V DDP MBC 45 P4.0 46 P4.1 47 P4.2 48 P0.7 1 Figure ...
Page 17
Pin Definitions and Functions The functions and default states of the XC87x external pins are provided in Table 3 Pin Definitions and Functions Symbol Pin Number (LQFP-64 / VQFN-48) P0 P0.0 17/12 P0.1 21/14 P0.2 18/13 Data Sheet Type ...
Page 18
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P0.3 63/1 P0.4 64/2 P0.5 1/3 P0.6 2/4 P0.7 62/48 Data Sheet Type Reset Function State Hi-Z SCK_1 COUT63_1 RXDO1_0 A17 Hi-Z MTSR_1 CC62_1 TXD1_0 A18 Hi-Z ...
Page 19
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P1 P1.0 34/25 P1.1 35/26 P1.2 36/27 P1.3 37/28 P1.4 38/29 Data Sheet Type Reset Function State I/O Port 1 Port 8-bit bidirectional general ...
Page 20
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P1.5 39/30 P1.6 10/9 P1.7 11/10 Data Sheet Type Reset Function State PU CCPOS0_1 EXINT5_0 T1_1 MRST_2 EXF2_0 RXDO_0 PU CCPOS1_1 T12HR_0 EXINT6_0 RXDC0_2 T21_1 PU CCPOS2_1 ...
Page 21
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P3 P3.0 43/33 P3.1 44/34 P3.2 49/35 P3.3 50/36 Data Sheet Type Reset Function State I/O Port 3 Port 8-bit bidirectional general purpose I/O ...
Page 22
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P3.4 51/37 P3.5 52/38 P3.6 41/32 P3.7 42/- Data Sheet Type Reset Function State Hi-Z CC62_0 RXDC0_1 T2EX1_0 T2CC3_1/ EXINT6_3 A14 Hi-Z COUT62_0 EXF21_0 TXDC0_1 A15 PU ...
Page 23
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P4 P4.0 59/45 P4.1 60/46 P4.2 61/47 P4.3 40/31 P4.4 45/- Data Sheet Type Reset Function State I/O Port 4 Port 8-bit bidirectional general ...
Page 24
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P4.5 46/- P4.6 47/- P4.7 48/- Data Sheet Type Reset Function State Hi-Z CCPOS1_3 T1_0 COUT61_2 T2CC3_0/ EXINT6_2 D5 Hi-Z CCPOS2_3 T2_0 CC62_2 T2CC4_0 D6 Hi-Z CTRAP_3 ...
Page 25
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P5 P5.0 8/- P5.1 9/- P5.2 12/- P5.3 13/- P5.4 14/- Data Sheet Type Reset Function State I/O Port 5 Port 8-bit bidirectional general ...
Page 26
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48) P5.5 15/- P5.6 19/- P5.7 20/- Data Sheet Type Reset Function State PU CCPOS2_0 CTRAP_1 CC60_3 TDO_1 TXD1_2 T2CC0_2/ EXINT3_3 A5 PU TCK_1 RXDO1_2 T2CC1_2/ EXINT4_3 A6 ...
Page 27
Table 3 Pin Definitions and Functions (cont’d) Symbol Pin Number (LQFP-64 / VQFN-48 25, 55/ DDP 17 26, 54/ SSP 18 6/8 DDC V 5/7 SSC V 32/23 AREF V 31/22 AGND AN0 22/- ...
Page 28
Functional Description Chapter 3 provides an overview of the XC87x functional description. 3.1 Processor Architecture The XC87x is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 ...
Page 29
Memory Organization The XC87x CPU operates in the following address spaces: • 8 Kbytes of Boot ROM program memory • 256 bytes of internal RAM data memory • 3 Kbytes of XRAM memory (XRAM can be read/written as program ...
Page 30
F’FFFF H Reserved 1'0000 H FFFF H External FEC0 H Reserved FE00 H External FC00 H XRAM 2 KByte F000 H D-Flash 4 KByte E000 H Boot ROM 8 KByte C000 H P-Flash 48 KByte / Reserved 8000 H P-Flash ...
Page 31
Memory Protection Strategy The XC87x memory protection strategy includes: • Basic protection: The user is able to block any external access via the boot option to any memory • Read-out protection: The user is able to protect the contents ...
Page 32
Table 4 Flash Protection Modes (cont’d) Flash Without hardware Protection protection P-Flash Possible program and erase D-Flash Read instructions in contents any program memory can be read by External Not possible access to D- Flash D-Flash Possible program D-Flash Possible ...
Page 33
Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range All registers, except the program counter, reside in the SFR area. The H H SFRs include pointers and ...
Page 34
SFR Data (to/from CPU) Figure 9 Address Extension by Mapping Data Sheet Standard Area (RMAP = 0) Module 1 SFRs SYSCON0.RMAP Module 2 SFRs rw Module n SFRs Mapped Area (RMAP = 1) Module (n+1) SFRs Module (n+2) SFRs Module ...
Page 35
SYSCON0 System Control Register Field Bits RMAP [7:5], 3,1 Note: The RMAP bit should be cleared/set by ANL or ORL instructions.The rest bits of SYSCON0 should not be modified. 3.2.2.2 Address ...
Page 36
SFR Address (from CPU) SFR Data (to/from CPU) Figure 10 Address Extension by Paging In order to access a register located in a page different from the actual one, the current page must be exited. This is done by reprogramming ...
Page 37
Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt ...
Page 38
The page register has the following definition: MOD_PAGE Page Register for module MOD Field Bits PAGE [2:0] STNR [5:4] Data Sheet STNR Type Description rw Page Bits When written, the ...
Page 39
Field Bits OP [7: 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11 bit field PASS opens access ...
Page 40
Password Register PASSWD Password Register 7 6 PASS Field Bits MODE [1:0] PROTECT_S 2 PASS [7:3] Data Sheet Type Description rw Bit Protection Scheme Control Bits 00 Scheme disabled - direct access to the protected ...
Page 41
XC87x Register Overview The SFRs of the XC87x are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Note: The addresses of the bitaddressable SFRs appear in bold typeface. 3.2.4.1 CPU ...
Page 42
Table 5 CPU Register Overview (cont’d) Addr Register Name 97 H MEXSP Reset Memory Extension Stack Pointer Register 98 H SCON Reset Serial Channel Control Register 99 H SBUF Reset Serial Data Buffer Register ...
Page 43
Table 6 MDU Register Overview (cont’d) Addr Register Name B1 H MDUCON Reset MDU Control Register B2 H MD0 Reset MDU Operand Register MR0 Reset MDU Result Register ...
Page 44
Table 7 CORDIC Register Overview (cont’d) Addr Register Name 9C H CD_CORDYL Reset CORDIC Y Data Low Byte 9D H CD_CORDYH Reset CORDIC Y Data High Byte 9E H CD_CORDZL Reset CORDIC Z Data ...
Page 45
Table 8 SCU Register Overview (cont’d) Addr Register Name B7 H EXICON0 Reset External Interrupt Control Register EXICON1 Reset External Interrupt Control Register NMICON Reset NMI Control Register ...
Page 46
Table 8 SCU Register Overview (cont’d) Addr Register Name BB H PASSWD Reset Password Register BE H COCON Reset Clock Output Control Register E9 H MISC_CON Reset Miscellaneous Control Register EA H PLL_CON1 Reset: ...
Page 47
WDT Registers The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 WDT Register Overview Addr Register Name RMAP = WDTCON Reset Watchdog Timer Control Register BC H ...
Page 48
Table 10 Port Register Overview (cont’d) Addr Register Name B0 H P3_DATA Reset Data Register B1 H P3_DIR Reset Direction Register C8 H P4_DATA Reset Data Register C9 H P4_DIR Reset: ...
Page 49
Table 10 Port Register Overview (cont’d) Addr Register Name 91 H P1_ALTSEL1 Reset Alternate Select 1 Register 92 H P5_ALTSEL0 Reset Alternate Select 0 Register 93 H P5_ALTSEL1 Reset Alternate Select ...
Page 50
ADC Registers The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 ADC Register Overview Addr Register Name RMAP = ADC_PAGE Reset Page Register RMAP = 0, PAGE ...
Page 51
Table 11 ADC Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE ADC_RESR0L Reset Result Register 0 Low CB H ADC_RESR0H Reset Result Register 0 High CC H ADC_RESR1L Reset ...
Page 52
Table 11 ADC Register Overview (cont’d) Addr Register Name CB H ADC_RCR1 Reset Result Control Register ADC_RCR2 Reset Result Control Register ADC_RCR3 Reset Result Control Register 3 CE ...
Page 53
Table 11 ADC Register Overview (cont’d) Addr Register Name CC H ADC_CRMR1 Reset Conversion Request Mode Register ADC_QMR0 Reset Queue Mode Register ADC_QSR0 Reset Queue Status Register 0 ...
Page 54
Timer 2 Compare/Capture Unit Registers The Timer 2 Compare/Capture Unit SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 T2CCU Register Overview Addr Register Name RMAP = T2_PAGE Reset ...
Page 55
Table 12 T2CCU Register Overview (cont’d) Addr Register Name C5 H T2CCU_CCTH Reset T2CCU Capture/Compare Timer Register High C6 H T2CCU_CCTCON Reset T2CCU CaptureCcompare Timer Control Register RMAP = 0, PAGE T2CCU_COSHDWReset: 00 ...
Page 56
Table 12 T2CCU Register Overview (cont’d) Addr Register Name RMAP = 0, PAGE T2CCU_CCTDTCLReset T2CCU Capture/Compare Timer Dead-Time Control Register Low C3 H T2CCU_CCTDTCHReset T2CCU Capture/Compare Timer Dead-Time Control Register High 3.2.4.9 Timer ...
Page 57
CCU6 Registers The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 CCU6 Register Overview Addr Register Name RMAP = CCU6_PAGE Reset Page Register RMAP = 0, PAGE ...
Page 58
Table 14 CCU6 Register Overview (cont’d) Addr Register Name FC H CCU6_CC61SRL Reset Capture/Compare Shadow Register for Channel CC61 Low FD H CCU6_CC61SRH Reset Capture/Compare Shadow Register for Channel CC61 High FE H CCU6_CC62SRL Reset: 00 ...
Page 59
Table 14 CCU6 Register Overview (cont’d) Addr Register Name FD H CCU6_CC61RH Reset Capture/Compare Register for Channel CC61 High FE H CCU6_CC62RL Reset Capture/Compare Register for Channel CC62 Low FF H CCU6_CC62RH Reset Capture/Compare ...
Page 60
Table 14 CCU6 Register Overview (cont’d) Addr Register Name FD H CCU6_MODCTRH Reset Modulation Control Register High FE H CCU6_TRPCTRL Reset Trap Control Register Low FF H CCU6_TRPCTRH Reset Trap Control Register High RMAP ...
Page 61
UART1 Registers The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 UART1 Register Overview Addr Register Name RMAP = SCON Reset Serial Channel Control Register C9 H ...
Page 62
Table 16 SSC Register Overview (cont’d) Addr Register Name AB H SSC_CONH Reset Control Register High Operating Mode AC H SSC_TBL Reset Transmitter Buffer Register Low AD H SSC_RBL Reset Receiver Buffer Register Low ...
Page 63
Table 18 OCDS Register Overview Addr Register Name RMAP = MMCR2 Reset Monitor Mode Control 2 Register EA H MEXTCR Reset Memory Extension Control Register EB H MMWR1 Reset Monitor Work ...
Page 64
Flash Registers The Flash SFRs can be accessed in the mapped memory area (RMAP = 1). Table 19 Flash Register Overview Addr Register Name RMAP = FCON Reset P-Flash Control Register D2 H EECON ...
Page 65
Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not ...
Page 66
... Data Sheet shows the Flash data retention and endurance targets for 1)2) Size Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 1)2) Size Kbytes 4 Kbytes 1 Kbytes 512 Bytes 256 Bytes 128 Bytes 59 XC87xCLM Functional Description Remarks SAF and SAX variant SAK variant Remarks V1.5, 2011-03 ...
Page 67
Flash Bank Pagination The XC87x product family offers Flash devices with either 64 Kbytes or 52 Kbytes of embedded Flash memory. Each Flash device consists of a Program Flash (P-Flash) and a single Data Flash (D-Flash) bank. P-Flash has ...
Page 68
Interrupt System The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC87x interrupt system provides extended ...
Page 69
Timer 0 Overflow Timer 1 Overflow UART Receive UART Transmit EINT0 EXINT0 EXICON0.0/1 EINT1 EXINT1 EXICON0.2/3 Bit-addressable Request flag is cleared by hardware Figure 13 Interrupt Request Sources (Part 1) Data Sheet TF0 TCON.5 ET0 IEN0.1 TF1 TCON.7 ET1 IEN0.3 ...
Page 70
Timer 2 TF2 Overflow T2_T2CON.7 T2EX EXF2 T2_T2CON.6 EXEN2 T2_T2CON.3 EDGES EL CCT T2_T2MOD.5 Overflow T2CCU_CCTCON.3 Normal Divider Overflow End of Syn Byte Syn Byte Error MultiCAN Node 0 ADC Service Request 0 ADC Service Request 1 MultiCAN Node 1 ...
Page 71
SSC Error SSC Transmit SSC Receive EINT2 EXINT2 EXICON0.4/5 RI UART1_SCON.0 UART1 TI UART1_SCON.1 Timer 21 TF2 Overflow T21_T2CON.7 T21EX T21_T2CON.6 EXEN2 T21_T2CON.3 EDGES EL UART1 Normal T21_T2MOD.5 Divider Overflow CORDIC MDU Result Ready MDU Error addressable Request flag is ...
Page 72
T2CC0/ EINT3 EXINT3 EXICON0.6/7 T2CC1/ EINT4 EXINT4 EXICON1.0/1 T2CC2/ EINT5 EXINT5 EXICON1.2/3 T2CC3/ EINT6 EXINT6 EXICON1.4/5 Compare Channel 4 CM4F T2CCU_COCON.4 Compare Channel 5 CM5F T2CCU_COCON.5 MultiCAN Node 3 Bit- addressable Request flag is cleared by hardware Figure 16 Interrupt ...
Page 73
CCU6 Interrupt node 0 CCU6SR0 IRCON3.0 MultiCAN Node 4 CANSRC4 IRCON3.1 CCU6 Interrupt node 1 CCU6SR1 IRCON3.4 MultiCAN Node 5 CANSRC5 IRCON3.5 CCU6 Interrupt node 2 CCU6SR2 IRCON4.0 MultiCAN Node 6 CANSRC6 IRCON4.1 CCU6 Interrupt node 3 CCU6SRC3 IRCON4.4 MultiCAN ...
Page 74
Interrupt Source and Vector Each interrupt event source has an associated interrupt vector address for the interrupt node it belongs to. This vector is accessed to service the corresponding interrupt node request. The interrupt service of each interrupt source ...
Page 75
Table 22 Interrupt Vector Addresses (cont’d) Interrupt Vector Source Address XINTR6 0033 H XINTR7 003B H XINTR8 0043 H XINTR9 004B H XINTR10 0053 H XINTR11 005B H XINTR12 0063 H XINTR13 006B H Data Sheet Assignment for XC87x MultiCAN ...
Page 76
Interrupt Priority An interrupt that is currently being serviced can only be interrupted by a higher-priority interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of the highest priority cannot be interrupted by ...
Page 77
Parallel Ports The XC87x has 40 port pins organized into five parallel ports: Port 0 (P0), Port 1 (P1), Port 3 (P3), Port 4 (P4) and Port 5 (P5). Each pin has a pair of internal pull-up and pull- ...
Page 78
Figure 18 shows the structure of a bidirectional port pin. Internal Bus Alternate Select Register 0 Alternate Select Register 1 AltDataOut 3 AltDataOut 2 AltDataOut1 AltDataIn Figure 18 General Structure of Bidirectional Port Data Sheet Px_PUDSEL Pull-up/Pull-down Select Register Pull-up/Pull-down ...
Page 79
Power Supply System with Embedded Voltage Regulator The XC87x microcontroller requires two different levels of power supply: • 3 5.0 V for the Embedded Voltage Regulator (EVR) and Ports • 2.5 V for the core, memory, on-chip ...
Page 80
Reset Control The XC87x has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC87x is first powered up, the status of certain pins (see defined to ensure proper ...
Page 81
Booting Scheme When the XC87x is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes ...
Page 82
... After the reset, the on-chip oscillator will be used by default.The external oscillator can be selected via software. In addition, the PLL provides a fail-safe logic to perform oscillator run and loss-of-lock detection. This allows emergency routines to be executed for system recovery or to perform system shut down. ...
Page 83
Wrapper PLL NR:1 OSC fosc OSCSS PDIV PLLPD Figure 20 CGU Block Diagram Direct Drive (PLL Bypass Operation) During PLL bypass operation, the system clock has the same frequency as the external clock source. PLL Mode The CPU clock is ...
Page 84
PLL mode. The PLL mode is used during normal system operation. System Frequency Selection For the XC87x, the value of NF, NR and OD can be selected by bits NDIV, PDIV and KDIV respectively for ...
Page 85
Oscillation measurement with the final target system is strongly recommended to verify the input amplitude at XTAL1 and to determine the actual oscillation allowance (margin negative resistance) for the oscillator-crystal system. When using an external clock signal, the ...
Page 86
Clock Management The CGU generates all clock signals required within the microcontroller from a single f clock, . During normal system operation, the typical frequencies of the different sys modules are as follow: • CPU clock: CCLK, SCLK = ...
Page 87
OSCSS External fosc OSC PLL On-chip OSC NF,NR,OD Figure 22 Clock Generation from Data Sheet CCCFG CORDIC CLK CORDIC MDUCCFG MDU CLK MDU CLKREL SD 1 FCLK /2 fsys 0 /3 COREL TLEN Toggle Latch f sys 80 XC87xCLM Functional ...
Page 88
For power saving purposes, the clocks may be disabled or slowed down according to Table 27. Table 27 System frequency ( Power Saving Mode Action Idle Clock to the CPU is disabled. Slow-down Clocks to the CPU and all the ...
Page 89
Power Saving Modes The power saving modes of the XC87x provide flexible power consumption through a combination of techniques, including: • Stopping the CPU clock • Stopping the clocks of individual system components • Reducing clock speed of some ...
Page 90
Watchdog Timer The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and recover from software or hardware failures. The WDT is reset at a regular interval that is predefined by the user. The CPU must ...
Page 91
If the WDT is not serviced before the timer overflow, a system malfunction is assumed result, the WDT NMI is triggered (assert FNMIWDT) and the reset prewarning is entered. The prewarning period lasts for 30 (assert WDTRST). The ...
Page 92
FFFF H WDTWINB WDTREL Figure 25 WDT Timing Diagram Table 28 lists the possible watchdog time ranges that can be achieved using a certain module clock. Some numbers are rounded to 3 significant digits. Table 28 Watchdog Time Ranges Reload ...
Page 93
Multiplication/Division Unit The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as shift and normalize features. It has been integrated to support the XC87x Core in real-time control applications, which require fast mathematical computations. ...
Page 94
CORDIC Coprocessor The CORDIC Coprocessor provides CPU with hardware support for the solving of circular (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions. Features • Modes of operation – Supports all CORDIC operating modes for solving circular (trigonometric), linear (multiply-add, ...
Page 95
Interrupt enabling and corresponding flag 3.13 UART and UART1 The XC87x provides two Universal Asynchronous Receiver/Transmitter (UART and UART1) modules for full-duplex asynchronous reception/transmission. Both are also receive-buffered, i.e., they can commence reception of a second byte before a ...
Page 96
Figure 26. FDM FDEN f f PCLK DIV Prescaler clk Figure 26 Baud-rate Generator Circuitry The baud rate timer is a count-down timer and ...
Page 97
The following formulas calculate the final baud rate without and with the fractional divider respectively: baud rate ---------------------------------------------------------------------------------- - where 2 = BRPRE × baud rate The maximum baud rate that can be generated is limited to clock ...
Page 98
Table 32 Deviation Error for UART with Fractional Divider enabled f Prescaling Factor PCLK (2BRPRE) 24 MHz 1 12 MHz 1 8 MHz 1 6 MHz 1 3.13.2 Baud Rate Generation using Timer 1 In UART modes 1 and 3 ...
Page 99
LIN Protocol The UART module can be used to support the Local Interconnect Network (LIN) protocol for both master and slave operations. The LIN baud rate detection feature, which consists of the hardware logic for Break and Synch Byte ...
Page 100
The header consists of a break and synch pattern followed by an identifier. Among these three fields, ...
Page 101
High-Speed Synchronous Serial Interface The High-Speed Synchronous Serial Interface (SSC) supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC internally (master mode), using its own 16-bit baud-rate generator, or can be received ...
Page 102
PCLK Baud-rate Generator Transmit Buffer Register TB Figure 28 SSC Block Diagram Data Sheet Clock Control Shift Clock RIR TIR SSC Control Block Register CON EIR Status Control Pin 16-Bit Shift Control Register Receive Buffer Register RB Internal Bus 95 ...
Page 103
Timer 0 and Timer 1 Timer 0 and Timer 1 can function as both timers or counters. When functioning as a timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 ...
Page 104
Timer 2 and Timer 21 Timer 2 and Timer 21 are 16-bit general purpose timers (THL2) that are fully compatible and have two modes of operation, a 16-bit auto-reload mode and a 16-bit one channel capture mode, see Table ...
Page 105
Timer 2 Capture/Compare Unit The T2CCU (Timer 2 Capture/Compare Unit) consists of the standard Timer 2 unit and a Capture/compare unit (CCU). The Capture/Compare Timer (CCT) is part of the CCU. Control is available in the T2CCU to select ...
Page 106
Capture/Compare Unit 6 The Capture/Compare Unit 6 (CCU6) provides two independent timers (T12, T13), which can be used for Pulse Width Modulation (PWM) generation, especially for AC-motor control. The CCU6 also supports special control modes for block commutation and ...
Page 107
T12 clock control start T13 interrupt control Figure 29 CCU6 Block Diagram Data Sheet module kernel compare channel 0 1 dead- channel 1 time 1 control channel 2 1 channel 3 compare input / output ...
Page 108
Controller Area Network (MultiCAN) The MultiCAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 B active. ...
Page 109
CAN functionality according to CAN specification V2.0 B active. • Dedicated control registers are provided for each CAN node. • A data transfer rate MBaud is supported. • Flexible and powerful message transfer control and error ...
Page 110
Analog-to-Digital Converter The XC87x includes a high-performance 10-bit Analog-to-Digital Converter (ADC) with eight multiplexed analog input channels. The ADC uses a successive approximation technique to convert the analog voltage levels from up to eight different sources. The analog input ...
Page 111
ADC f ADCA Figure 31 ADC Clocking Scheme f For module clock = 24 MHz, the analog clock ADC shown in Table 35. f Table 35 Frequency Selection ADCI f Module Clock CTC ADC 24 MHz 00 ...
Page 112
Synchronization phase ( t • Sample phase ( ) S • Conversion phase t • Write result phase ( WR conversion start trigger Sample Phase f ADCI BUSY Bit SAMPLE Bit t SYN Figure 32 ADC Conversion Timing Data ...
Page 113
On-Chip Debug Support The On-Chip Debug Support (OCDS) provides the basic functionality required for the software development and debugging of XC800-based systems. The OCDS design is based on these principles: • Use the built-in debug functionality of the XC800 ...
Page 114
JTAG Module TMS TCK Debug JTAG TDI Interface TDO MBC Monitor & Bootstrap loader Control line Suspend Control System Control Reset Unit Clock - parts of OCDS Figure 33 OCDS Block Diagram 3.23.1 JTAG ID Register This is a read-only ...
Page 115
Chip Identification Number The XC87x identity (ID) register is located at Page 1 of address B3 register However, for easy identification of product variants, the Chip H Identification Number, which is an unique number assigned to ...
Page 116
Table 37 Chip Identification Number (cont’d) Product Variant XC874CM-13FV 5V XC874LM-13FV 5V XC874-13FV 5V Data Sheet Chip Identification Number AC-step 4B590402 H 4B510422 H 4B590462 H 109 XC87xCLM Functional Description V1.5, 2011-03 ...
Page 117
Electrical Parameters Chapter 4 provides the characteristics of the electrical parameters which are implementation-specific for the XC87x. 4.1 General Parameters The general parameters are described here to aid the users in interpreting the parameters mainly in Section 4.2 4.1.1 ...
Page 118
Absolute Maximum Rating Maximum ratings are the extreme limits to which the XC87x can be subjected to without permanent damage. Table 38 Absolute Maximum Rating Parameters Parameter Ambient temperature Storage temperature Junction temperature Voltage on power supply pin with ...
Page 119
... Symbol Limit Values min. max. V 4.5 5.5 DDP V 3.0 3.6 DDP 26.67 CCLK T - -40 105 -40 125 Figure 22 110 XC87xCLM Electrical Parameters Unit Notes/ Conditions V 5V Device V 3.3V Device V 2) MHz °C SAF-XC878/874... °C SAX-XC878... °C SAK-XC878/874... for detailed description. V1.5, 2011-03 ...
Page 120
DC Parameters The electrical characteristics of the DC Parameters are detailed in this section. 4.2.1 Input/Output Characteristics Table 40 provides the characteristics of the input/output pins of the XC87x. Table 40 Input/Output Characteristics (Operating Conditions apply) Parameter Symbol V ...
Page 121
Table 40 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol I Maximum current per V pin (excluding DDP V and ) SS Σ| Maximum current for all pins (excluding V V and ) DDP SS I Maximum current into V ...
Page 122
Table 40 Input/Output Characteristics (Operating Conditions apply) (cont’d) Parameter Symbol V Voltage on any pin V during power off DDP I Maximum current per V pin (excluding DDP V and ) SS Σ| Maximum current for all pins (excluding V ...
Page 123
Supply Threshold Characteristics Table 41 provides the characteristics of the supply threshold in the XC87x. 5.0V VDDP 2.5V VDDC V DDCPOR Figure 34 Supply Threshold Parameters Table 41 Supply Threshold Parameters (Operating Conditions apply) Parameters 1) V brownout voltage ...
Page 124
ADC Characteristics The values in the table below are given for an analog power supply between 4 5.5 V. The ADC can be used with an analog power supply down But in this case, ...
Page 125
Table 42 ADC Characteristics (Operating Conditions apply; Parameter Symbol R Input resistance of AREF the reference input R Input resistance of AIN the selected analog channel 1) Not subjected to production test, verified by design/characterization. 2) This value includes the ...
Page 126
R EXT V C AIN EXT V AREF Figure 35 ADC Input Circuits 4.2.3.1 ADC Conversion Timing t t Conversion time ADC r = CTC + 2 for CTC = for CTC = 11 ...
Page 127
... SAK variant 4) mA SAF and SAX variants 4) mA SAK variant 5) mA SAF and SAX variants 5) mA SAK variant 6) mA SAF and SAX variants 6) mA SAK variant = + 105 °C and 5.5 V). A DDP V ; all other pins are disconnected, no DDP , RESET = B V1.5, 2011-03 V ...
Page 128
... Power Down Current Parameter Range DDP Power-Down Mode 1) The table is only applicable to SAF and SAX variants. SAK variant does not support power-down mode I 2) The typical values are based on preliminary measurements and are to be used as reference only. These PDP V values are measured at ...
Page 129
... Active Mode Idle Mode Active Mode with slow-down enabled Idle Mode with slow-down enabled 1) The table is only applicable to SAF and SAX variants The typical values are based on preliminary measurements and are to be used as reference only. These DDP values are periodically measured at ...
Page 130
... Table 46 Power Down Current range) Parameter V = 3.3V Range DDP Power-Down Mode 1) The table is only applicable to SAF and SAX variants The typical values are based on preliminary measurements and are to be used as reference only. These PDP V values are measured at DDP I 3) The maximum ...
Page 131
AC Parameters The electrical characteristics of the AC Parameters are detailed in this section. 4.3.1 Testing Waveforms The testing waveforms for rise/fall time, output delay and output high impedance are shown in Figure 36, Figure 37 V DDP 10% ...
Page 132
Output Rise/Fall Times Table 47 provides the characteristics of the output rise/fall times in the XC87x. Table 47 Output Rise/Fall Times Parameters (Operating Conditions apply) Parameter Range DDP Rise/fall times V = 3.3V Range DDP Rise/fall ...
Page 133
Power-on Reset and PLL Timing Table 48 provides the characteristics of the power-on reset and PLL timing in the XC87x. Table 48 Power-On Reset and PLL Timing (Operating Conditions apply) Parameter Symbol t On-Chip Oscillator start-up time t PLL ...
Page 134
On-Chip Oscillator Characteristics Table 49 provides the characteristics of the on-chip oscillator in the XC87x. Table 49 On-chip Oscillator Characteristics (Operating Conditions apply) Parameter Symbol f Nominal frequency NOM ∆ f Long term frequency LT deviation ∆ f Short ...
Page 135
External Data Memory Characteristics Table 50 shows the timing of the external data memory read cycle. Table 50 External Data Memory Read Timing Parameter Symbol t RD pulse width t Address valid valid data ...
Page 136
Table 51 shows the timing of the external data memory write cycle. Table 51 External Data Memory Write Timing Parameter WR pulse width Address valid to WR Data valid to WR transition Data setup before WR Data hold after WR ...
Page 137
External Clock Drive XTAL1 Table 52 shows the parameters that define the external clock supply for XC87x. These timing parameters are based on the direct XTAL1 drive of clock input signals. They are not applicable if an external crystal ...
Page 138
JTAG Timing Table 53 provides the characteristics of the JTAG timing in the XC87x. Table 53 TCK Clock Timing (Operating Conditions apply pF) Parameter TCK clock period TCK high time TCK low time TCK clock rise ...
Page 139
Table 54 JTAG Timing (Operating Conditions apply pF) (cont’d) Parameter TDO high impedance to valid output from TCK TDO valid output to high impedance from TCK 1) Not all parameters are 100% tested, but are verified by ...
Page 140
SSC Master Mode Timing Table 55 provides the characteristics of the SSC timing in the XC87x. Table 55 SSC Master Mode Timing (Operating Conditions apply pF) Parameter SCLK clock period MTSR delay from SCLK MRST setup ...
Page 141
Package and Quality Declaration Chapter 5 provides the information of the XC87x package and reliability section. 5.1 Package Parameters Table 56 provides the thermal characteristics of the package used in XC878 and XC874. Table 56 Thermal Characteristics of the ...
Page 142
Package Outline Figure 47 shows the package outlines of the XC878. Figure 47 PG-LQFP-64-4 Package Outline Data Sheet Package and Quality Declaration 134 XC87xCLM V1.5, 2011-03 ...
Page 143
Figure 48 shows the package outlines of the XC874. Figure 48 PG-VQFN-48-22 Package Outline Data Sheet Package and Quality Declaration 135 XC87xCLM V1.5, 2011-03 ...
Page 144
Quality Declaration Table 57 shows the characteristics of the quality parameters in the XC87x. Table 57 Quality Parameters Parameter Operation Lifetime when the device is used at the 1) two stated T J Operation Lifetime when the device is ...
Page 145
... Published by Infineon Technologies AG ...