SAF-XC866-4FRI BE Infineon Technologies, SAF-XC866-4FRI BE Datasheet - Page 73

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SAF-XC866-4FRI BE

Manufacturer Part Number
SAF-XC866-4FRI BE
Description
IC MCU 8BIT 12KB FLASH 38TSSOP
Manufacturer
Infineon Technologies
Series
XC8xxr
Datasheet

Specifications of SAF-XC866-4FRI BE

Core Processor
XC800
Core Size
8-Bit
Speed
86MHz
Connectivity
SSI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
38-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
• 8-bit reload value (BR_VALUE) for the baud rate timer defined by register BG
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
The maximum baud rate that can be generated is limited to
clock of 26.7 MHz, the maximum achievable baud rate is 0.83 MBaud.
Standard LIN protocal can support a maximum baud rate of 20kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20kHz to 115.2kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 26
settings and deviation errors. The fractional divider is disabled and a module clock of
26.7 MHz is used.
Table 26
Baud rate
19.2 kBaud
9600 Baud
4800 Baud
2400 Baud
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated.
Data Sheet
baud rate
lists the various commonly used baud rates with their corresponding parameter
=
Table 27
---------------------------------------------------------------------------------- - where 2
16 2
Typical Baud rates for UART with Fractional Divider disabled
×
baud rate
BRPRE
lists the resulting deviation errors from generating a baud rate of
Prescaling Factor
(2
1 (BRPRE=000
1 (BRPRE=000
2 (BRPRE=001
4 (BRPRE=010
BRPRE
×
f
=
PCLK
(
BR_VALUE
---------------------------------------------------------------------------------- -
16 2
)
×
BRPRE
B
B
B
B
)
)
)
)
+
×
f
69
PCLK
1
(
)
BR_VALUE
Reload Value
(BR_VALUE + 1)
174 (AE
174 (AE
174 (AE
87 (57
H
H
H
H
)
BRPRE
)
)
)
+
f
PCLK
1
)
×
×
Functional Description
/32. Hence, for a module
STEP
-------------- -
(
256
BR_VALUE
Deviation Error
-0.22 %
-0.22 %
-0.22 %
-0.22 %
V1.2, 2007-10
+
1
XC866
) 1
>

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