MAXQ610A-0000+ Maxim Integrated Products, MAXQ610A-0000+ Datasheet - Page 17

• Manufacturer Part Number: MAXQ610A-0000+
• Description: IC MCU 16BIT 64K IR MOD 32TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ610A-0000+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 12MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-TQFN Exposed Pad
• Processor Series: MAXQ610
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART
• Maximum Clock Frequency: 12 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 1.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Controller Family/series: MAXQ
• No. Of I/o's: 24
• Ram Memory Size: 2048Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Embedded Interface Type: JTAG, SPI, USART
• Rohs Compliant: Yes
• Number Of Programmable I/os: 32
• Development Tools By Supplier: MAXQ610-KIT
• Package: 32TQFN EP
• Family Name: MAXQ
• Maximum Speed: 12 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 90-M6800+B01

When RXBCNT = 1, the IRV capture operation is dis-
abled and the interrupt flag associated with the capture
no longer denotes a capture. In the carrier burst-count
mode, the IRMT register is now used only to count quali-
fied edges. The IRIF interrupt flag (normally used to sig-
nal a capture when RXBCNT = 0) now becomes set if
ever two IRCA cycles elapse without getting a qualified
edge. The IRIF interrupt flag thus denotes absence of
the carrier and the beginning of a space in the receive
signal. When the RXBCNT bit is changed from 0 to 1,
the IRMT register is set to 0001h. The IRCFME bit is still
used to define whether the IRV register is counting sys-
tem IRCLK clocks or IRCA-defined carrier cycles. The
IRXRL bit is still used to define whether the IRV register
is reloaded with 0000h on detection of a qualified edge
(per the IRXSEL[1:0] bits). Figure 6 and the descriptive
sequence embedded in the figure illustrate the expect-
ed usage of the receive burst-count mode.
The MAXQ610 provides two timers/counters that sup-
port the following functions:
• 16-bit timer/counter
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
The MAXQ610 provides port pins for general-purpose
I/Os that have the following features:
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to V
Table 3. USART Mode Details
mode
Mode 0
Mode 1
Mode 2
Mode 3
MODE
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________
16-Bit Timers/Counters
General-Purpose I/O
DD
Asynchronous
Asynchronous
Asynchronous
Synchronous
when operating in input
TYPE
START BITS
N/A
1
1
1
While the microcontroller is in a reset state, all port pins
become high impedance with weak pullups disabled,
unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-pur-
pose I/O pins when the special functions are disabled.
For a detailed description of the special functions avail-
able for each pin, refer to the part-specific user manual.
The MAXQ Family User’s Guide: MAXQ610 Supplement
describes all special functions available on the
MAXQ610.
The USART units are implemented with the following
characteristics:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• Programmable interrupt for receive and transmit
• Independent baud-rate generator
• Programmable 9th bit parity support
• Start/stop bit support
The integrated SPI provides an independent serial
communication channel that communicates synchro-
nously with peripheral devices in a multiple master or
multiple slave system. The interface allows access to a
4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
is provided when two or more masters attempt a data
transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2.
When operating as an SPI slave, the MAXQ610 can
support up to a Sysclk/4 SPI transfer rate. Data is trans-
ferred as an 8-bit or 16-bit value, MSB first. In addition,
the SPI module supports configuration of active SSEL
state through the slave active select.
Serial Peripheral Interface (SPI)
DATA BITS
8 + 1
8 + 1
8
8
STOP BITS
N/A
1
1
1
USART
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