MAXQ610A-0000+ Maxim Integrated Products, MAXQ610A-0000+ Datasheet - Page 10
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MAXQ610A-0000+
Manufacturer Part Number
MAXQ610A-0000+
Description
IC MCU 16BIT 64K IR MOD 32TQFN
Manufacturer
Maxim Integrated Products
Series
MAXQ™r
Datasheets
1.MAXQ610A-0000.pdf
(28 pages)
2.MAXQ610A-0000.pdf
(29 pages)
3.MAXQ610A-0000.pdf
(23 pages)
Specifications of MAXQ610A-0000+
Core Processor
RISC
Core Size
16-Bit
Speed
12MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
Number Of I /o
20
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
32-TQFN Exposed Pad
Processor Series
MAXQ610
Core
RISC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
SPI, USART
Maximum Clock Frequency
12 MHz
Number Of Timers
4
Operating Supply Voltage
1.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Controller Family/series
MAXQ
No. Of I/o's
24
Ram Memory Size
2048Byte
Cpu Speed
12MHz
No. Of Timers
2
Embedded Interface Type
JTAG, SPI, USART
Rohs Compliant
Yes
Number Of Programmable I/os
32
Development Tools By Supplier
MAXQ610-KIT
Package
32TQFN EP
Family Name
MAXQ
Maximum Speed
12 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
90-M6800+B01
16-Bit Microcontroller with Infrared Module
10
32 TQFN
24–27
23
—
______________________________________________________________________________________
PIN
28, 33, 34
40 TQFN
2, 4, 15,
25, 26,
29–32,
16, 27,
35, 36
—
44 TQFN
2, 4, 15,
27, 29,
32–35,
16, 30,
31, 36,
38, 39
37
—
TCK, TDI,
NAME
SCLK,
MOSI,
MISO,
INT8–
INT15
P2.0–
SSEL,
P3.0–
P2.7;
TMS,
P3.7;
TDO
N.C.
General-Purpose, Digital, I/O, Type-C Port. These port pins function as
bidirectional I/O pins. P2.0–P2.3 default to high-impedance mode after a reset.
Software must configure these pins after release from reset to remove the high-
impedance input condition. All alternate functions must be enabled from
software. Enabling the pin’s special function disables the general-purpose I/O
on the pin.
The JTAG pins (P2.4–P2.7) default to their JTAG function with weak pullups
enabled after a reset. The JTAG function can be disabled using the TAP bit in
the SC register.
P2.7 functions as the JTAG test-data output on reset and defaults to an input
with a weak pullup. The output function of the test data is only enabled during
the TAP’s Shift_IR or Shift_DR states.
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.
These port pins function as bidirectional I/O pins or as interrupts. All port pins
default to high-impedance mode after a reset. Software must configure these
pins after release from reset to remove the high-impedance input condition. All
interrupt functions must be enabled from software.
No Connection. Reserved for future use. Leave this pin unconnected.
32 TQFN
32 TQFN
—
—
—
—
24
25
26
27
—
—
—
—
—
—
—
—
NO CONNECTION PINS
40 TQFN
40 TQFN
25
26
29
30
31
32
35
36
15
16
27
28
33
34
2
4
44 TQFN
44 TQFN
27
29
32
33
34
35
38
39
15
16
30
31
36
37
2
4
Pin Description (continued)
FUNCTION
PORT
PORT
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
SPECIAL FUNCTION
SPECIAL FUNCTION
INT10
INT11
INT12
INT13
INT14
INT15
SCLK
MOSI
MISO
SSEL
INT8
INT9
TCK
TMS
TDO
TDI