UPD78F9200MA-CAC-A Renesas Electronics America, UPD78F9200MA-CAC-A Datasheet - Page 70

• Manufacturer Part Number: UPD78F9200MA-CAC-A
• Description: MCU 8BIT 1KB FLASH 128B RAM
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9200MA-CAC-A

• Package / Case: *
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 10MHz
• Number Of I /o: 7
• Core Processor: 78K0S
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Program Memory Size: 1KB (1K x 8)
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Peripherals: LVD, POR, PWM, WDT
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

68
Address: FF02H, After reset: 00H (Output latch) R/W
Symbol
P2
Address: FF03H, After reset: 00H
Symbol
P3
Address: FF04H, After reset: 00H (Output latch) R/W
Symbol
P4
(2) Port registers (P2 to P4)
(3) Port mode control register 2 (PMC2) (
These registers are used to write data to be output from the corresponding port pin to an external device
connected to the chip.
When a port register is read, the pin level is read in the input mode, and the value of the output latch of the
port is read in the output mode.
P20 to P23, P32, P40 and P43 are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
This register specifies the port/alternate function (except the A/D converter function) mode or the A/D
converter mode.
Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units.
PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PMC2 to 00H.
Note Because P34 is read-only, its reset value is undefined.
Pmn
7
0
7
0
7
0
0
1
Output 0
Output 1
Controls of output data (in output mode)
6
0
6
0
6
0
Note
(Output latch) R/W
Figure 4-13. Format of Port Register
5
0
5
0
5
0
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18172EJ3V0UD
PD78F920x only
Note
P34
4
0
4
4
0
m = 2 to 4; n = 0 to 4
)
P23
P43
3
3
0
3
Input low level
Input high level
Input data read (in input mode)
P22
P32
2
2
2
0
P21
1
1
0
1
0
P20
P40
0
0
0
0