HD6417760BP200AD Renesas Electronics America, HD6417760BP200AD Datasheet - Page 679

• Manufacturer Part Number: HD6417760BP200AD
• Description: IC SUPERH MPU ROMLESS 256BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417760BP200AD

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. Reserved bit in channel 0.
Bit
5
4
3
2
1
0
2. Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set.
3. SCIF_CTS is fixed at active-0 regardless of the input value, and SCIF_RTS output is
4. A reset operation is performed in the event of a power-on reset or manual reset.
Bit Name
TTRG1
TTRG0
MCE
TFRST
RFRST
LOOP
also fixed at 0.
*
1
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit FIFO Data Number Trigger
These bits are used to set the number of
remaining transmit data bytes that sets the TDFE
flag in SCFSR. The TDFE flag is set when the
number of transmit data bytes in SCFTDR is equal
to or less than the trigger set number shown
below.
00:64 (64)
01:32 (96)
10:4 (124)
11:0 (128)
Modem Control Enable
Enables the SCIF_CTS and SCIF_RTS modem
control signals. Always set the MCE bit to 0 in
synchronous mode.
0: Modem signals disabled*
1: Modem signals enabled
Transmit FIFO Data Register Reset
Invalidates the transmit data in the transmit FIFO
data register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Receive FIFO Data Register Reset
Invalidates the receive data in the receive FIFO
data register and resets it to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Loopback Test
Internally connects the transmit output pin
(SCIF_TXD) and receive input pin (SCIF_RXD),
and the SCIF_RTS pin and SCIF_CTS pin,
enabling loopback testing.
0: Loopback test disabled
1: Loopback test enabled
Rev. 2.00 Feb. 12, 2010 Page 595 of 1330
*
2
3
4
4
REJ09B0554-0200