M30803FGFP#U5 Renesas Electronics America, M30803FGFP#U5 Datasheet - Page 79
M30803FGFP#U5
Manufacturer Part Number
M30803FGFP#U5
Description
MCU 3/5V 256K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6
Figure 9.5 Interrupt response time
1 .
0
C
9.11 Interrupt Sequence
9.12 Interrupt Response Time
9
0 .
8 /
B
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SCMPU, SIN, SMOVB, SMOVF, SMOVU,
SSTR, SOUT or RMPA instruction, the processor temporarily suspends the instruction being executed,
and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt se-
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
(4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. Saves in the
(5) Saves the content of the program counter (PC) in the stack area. Saves in the PC save register
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 9.5 shows the interrupt response time.
0
0
0
1
A
8
G
address 000000
request bit is "0".
quence in the temporary register (Note) within the CPU.
to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
flag save register (SVF) in high-speed interrupt.
(SVP) in high-speed interrupt.
u
7
o r
Interrupt request generated
. g
0 -
(a) The period from the occurrence of an interrupt to the completion of the instruction under execution.
(b) The time required for executing the interrupt sequence.
u
1
0
p
0
, 2
0
2
0
0
5
Page 66
16
(address 000002
Instruction
f o
3
2
Interrupt response time
9
(a)
Interrupt request acknowledged
16
Interrupt sequence
when high-speed interrupt). After this, the related interrupt
(b)
Instruction in interrupt
routine
9. Interrupt Outline
Time
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