M306N4FGTFP Renesas Electronics America, M306N4FGTFP Datasheet - Page 125
M306N4FGTFP
Manufacturer Part Number
M306N4FGTFP
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/6Nr
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M306N4FGGPU3.pdf
(94 pages)
3.M306N4FGGPU3.pdf
(414 pages)
Specifications of M306N4FGTFP
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Price
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M306N4FGTFP
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TI
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M306N4FGTFP
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RENESAS
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M306N4FGTFP
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10 000
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M306N4FGTFP
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RENESAS/瑞萨
Quantity:
20 000
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Part Number:
M306N4FGTFP#UKJ
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Renesas Electronics America
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Part Number:
M306N4FGTFP#UKJ
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 12.5 Transfer Cycles for Source Read
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
(3) When the source read cycle under condition (1) has one wait state inserted
(4) When the source read cycle under condition (2) has one wait state inserted
NOTE:
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
1. The same timing changes occur with the respective conditions at the destination as at the source.
transfer unit is 16 bits and an 8-bit bus is used
Apr 14, 2006
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
page 101 of 376
CPU use
CPU use
Source
Source
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
Dummy
cycle
cycle
Destination
Dummy
cycle
Dummy
cycle
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
cycle
Dummy
cycle
CPU use
CPU use
12. DMAC
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