HD64F3337YCP16V Renesas Electronics America, HD64F3337YCP16V Datasheet - Page 502
HD64F3337YCP16V
Manufacturer Part Number
HD64F3337YCP16V
Description
MCU 3/5V 60K PB-FREE 84-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Specifications of HD64F3337YCP16V
Core Size
8-Bit
Program Memory Size
60KB (60K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Operating Temperature
-20°C ~ 75°C
Package / Case
84-PLCC
No. Of I/o's
74
Ram Memory Size
1KB
Cpu Speed
16MHz
No. Of Timers
6
No. Of Pwm Channels
2
Digital Ic Case Style
PLCC
Controller Family/series
H8/300
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Price
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
COILMASTER
Quantity:
30 000
Company:
Part Number:
HD64F3337YCP16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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For NMI interrupts while flash memory is being programmed or erased, these malfunction and
runaway problems can be prevented by using the RAM overlap function with the settings
described below.
1. Do not store the NMI interrupt-handling routine
2. Set the NMI interrupt vector in address H'F806 in RAM (corresponding to H'0006 in flash
3. After the above settings, set both the RAMS and RAM0 bits to 1 in WSCR.
Due to the setting of step 3, if an interrupt signal is input while 12 V is applied to the FV
RAM overlap function is enabled and part of the RAM (H'F800 to H'F87F) is overlapped onto the
small-block area of flash memory (H'0000 to H'007F). As a result, when an interrupt is input, the
vector is read from RAM, not flash memory, so the interrupt is handled normally even if flash
memory is being programmed or erased. This can prevent malfunction and runaway.
Notes: *1 When the interrupt mask bit (I) of the condition control register (CCR) is set to 1, all
Notes on Interrupt Handling in Boot Mode: In boot mode, the settings described above
concerning NMI interrupts are carried out, and NMI interrupt handling (but not other interrupt
handling) is enabled while the boot program is executing. Note the following points concerning
the user program.
472
H'EF7F in mode2. nor H'0000 to H'F77F in mode3). Store it elsewhere (in RAM, for example)
memory).
If interrupt handling is required
If interrupt handling is not required
Since the RAMS and RAM0 bits remain set to 1 in WSCR, make sure that the user program
disables the RAM overlap by clearing the RAMS and RAM0 bits both to 0.
Load the NMI vector (H'F780) into address H'F806 in RAM (the 38th byte of the
The interrupt handling routine used by the boot program is stored in addresses H'F780 to
transferred user program should be H'F780).
H'F78F in RAM. Make sure that the user program does not overwrite this area.
*2 The vector table might not be read correctly for one of the following reasons:
*3 This routine should be programmed so as to prevent microcontroller runaway.
*4 For details on WSCR settings, see section 20.2.4, Wait-State Control Register.
interrupts except NMI are masked. For details see (2) in section 2.2.2, Control
Registers.
• If flash memory is read while it is being programmed or erased (while the P or E bit
• If no value has been written for the NMI entry in the vector table yet, NMI
of FLMCR is set), the correct value cannot be read.
exception handling will not be executed correctly.
*3
in the flash memory area (neither H'0000 to
*4
PP
pin, the
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