HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1418
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Quantity
Price
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Part Number:
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Appendix B Internal I/O Register
TIOR0L—Timer I/O Control Register 0L
Page 1368 of 1458
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
Bit
Initial value
Read/Write
Notes: 1.
TGR0D I/O Control
register operates as a buffer register.
0
1
0
1
0
1
2.
0
*
1
0
1
0
1
When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register,
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD3
R/W
TGR0D is
output
compare
register *
TGR0D is
input
capture
register *
7
0
2
2
Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register,
TGR0C I/O Control
0
1
IOD2
R/W
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
6
0
0
1
0
1
0
*
1
0
1
0
1
this setting is invalid and input capture/output compare is not generated.
0
1
0
1
0
1
0
1
0
1
*
*
IOD1
R/W
TGR0C is
output
compare
register*
TGR0C is
input
capture
register *
5
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down *
1
1
IOD0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCC0 pin
Capture input
source is channel
1/count clock
R/W
4
0
1
H'FF13
IOC3
R/W
3
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*: Don't care
IOC2
R/W
2
0
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
IOC1
R/W
1
0
*: Don't care
IOC0
R/W
0
0
May 28, 2010
TPU0
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