HD64F3437STF16V Renesas Electronics America, HD64F3437STF16V Datasheet - Page 251
HD64F3437STF16V
Manufacturer Part Number
HD64F3437STF16V
Description
MCU 3/5V 60K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300r
Datasheet
1.HD64F3437STF16V.pdf
(755 pages)
Specifications of HD64F3437STF16V
Core Processor
H8/300
Core Size
8-Bit
Speed
16MHz
Connectivity
Host Interface, I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
74
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3437STF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3437STF16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Positive Logic (OS = 0):
1. When (OE = 0)—(a) in Figure 10.3
2. When (OE = 1)
Negative Logic (OS = 1)—(e) in Figure 10.3: The operation is the same except that high and low
are reversed in the PWM output. [(e) in figure 10.3]
10.4
Some notes on the use of the PWM timer module are given below.
1. Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
2. If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at 0.
The timer count is held at H'00 and PWM output is inhibited. [Pin 4
PW1) is used for port 4 input/output, and its state depends on the corresponding port 4 data
register and data direction register.] Any value (such as N in figure 10.3) written in the DTR
becomes valid immediately.
a. The timer counter begins incrementing. The PWM output goes high when TCNT changes
b. When the count passes the DTR value, the PWM output goes low. [(c) in figure 10.3]
c. If the DTR value is changed (by writing the data “M” in figure 10.3), the new value
should be made before the output enable bit (OE) is set to 1.
If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant at
1.
(For positive logic, 0 is low and 1 is high. For negative logic, 0 is high and 1 is low.)
from H'00 to H'01, unless DTR = H'00. [(b) in figure 10.3]
becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 10.3]
Application Notes
6
(for PW0) or pin 4
7
(for
219
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