HD6473937RXV Renesas Electronics America, HD6473937RXV Datasheet - Page 397
HD6473937RXV
Manufacturer Part Number
HD6473937RXV
Description
MCU 3/5V 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet
1.HD6473937RXV.pdf
(523 pages)
Specifications of HD6473937RXV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473937RXV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The following describes the sequence of events between the Host and the FLEX decoder required
to handle a temporary address:
Following an Address Packet, the host will receive a Vector Packet with V
i
to this pager). The system may send either and i
assigning a temporary address. The vector packet with and i
temporary address is assigned and the frame in which the temporary address is expected. The
vector packet with and i
of the expected frame (essentially indicating 64 frames in which to look for the temporary
address), and a message sequence number. When the vector packet with and i
received on a long address, the specific assign frame is included in the mes-sage word sent
after the vector.
The FLEX decoder will increment the corresponding temporary address counter for each
temporary address assignment vector received and begin to decode all of the follow-ing
frames. Note that this implies a single dynamic group assignment that is implemented by
sending two short instructions (one for each temporary address assignment mode of the short
instruction vector) will cause the corresponding temporary address counter to incre-ment
twice.
The FLEX decoder continues to decode all of the frames and passes any address infor-mation,
vector information and message information to the host followed by a status packet indicating
the end of each frame and the current frame number.
There are several scenarios which may occur with temporary addresses.
1
i
0
1. The temporary address is not found in the any of the assigned frames and therefore the
2. The temporary address is found in the frame it was assigned and was not a fragmented
3. The temporary address is found in the assigned frame and it is a fragmented message.
= 000 or 010 (a Short Instruction Vector indicating a temporary address has been assigned
host must terminate the temporary address mode by sending an All Frame Mode Packet
to the FLEX decoder with the “DTA” bit of the particular temporary address set (if both
temporary address assignment packets were used to assign the temporary address, the
“DTA” bit must be set twice to disable the temporary address).
message. Again, the host must terminate the temporary address mode by sending an All
Frame Mode Packet to the FLEX decoder with the “DTA” bit of the particular
temporary address set (if both temporary address assignment packets were used to
assign the temporary address, the “DTA” bit must be set twice to disable the temporary
address).
In this case, the host must follow the rules for Operation of a Fragmented Message and
determine the proper time to stop the all frame mode operation. In this case, the host
must write to the “DAF” bit with a “1” and the appropriate “DTA” bit with a “1” in the
All Frame Mode Register in order to terminate both the fragmented message and the
temporary address (if both temporary address assignment packets were used to assign
the temporary address, the “DTA” bit must be set twice to disable the temporary
address).
2
i
1
i
0
= 010 will indicate which temporary address is assigned, the MSb
2
i
1
i
0
= 000 or and i
2
i
1
i
0
= 000 will indicate which
2
i
1
i
0
= 010 or both when
2
V
2
1
i
V
1
i
0
0
= 001 and i
= 010 is
383
2
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