MCF5282CVF66J Freescale Semiconductor, MCF5282CVF66J Datasheet - Page 754
MCF5282CVF66J
Manufacturer Part Number
MCF5282CVF66J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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GPIO
H
Halt, fault-on-fault 30-17
HIGHZ instruction 31-8
Index-6
registers
reset 20-21
block diagram 26-2
electrical characteristics
features 26-4
initialization 26-28
memory map 26-7
operation 26-4
overview 26-1
registers
timing diagrams 33-19
gated time accumulation 20-19
channel (GPTCn) 20-13
compare force (GPCFORC) 20-6
control 1–2 (GPTCTLn) 20-9
counter (GPTCNT) 20-7
flag 1–2 (GPTFLGn) 20-12
input capture/output compare select (GPTIOS) 20-5
interrupt enable (GPTIE) 20-10
output compare 3 data (GPTOC3D) 20-7
output compare 3 mask (GPTOC3M) 20-6
port data (PORTTn) 20-16
port data direction (GPTDDR) 20-17
pulse accumulator control (GPTPACTL) 20-14
pulse accumulator counter (GPTPACNT) 20-16
pulse accumulator flag (GPTPAFLG) 20-15
system control 1–2 (GPTSCRn) 20-8
toggle-on-overflow (GPTTOV) 20-9
timing 33-18
low-power modes 7-9
port AS pin assignment (PASPAR) 26-21
port B/C/D pin assignment (PBCDPAR) 26-16
port clear output data (CLRn) 26-14
port data direction (DDRn) 26-11
port E pin assignment (PEPAR) 26-17
port EH/EL pin assignment (PEHLPAR) 26-22
port F pin assignment (PFPAR) 26-19
port J pin assignment (PJPAR) 26-20
port output data (PORTn) 26-10
port pin data/set data (PORTnP/SETn) 26-13
port QS pin assignment (PQSPAR) 26-23
port SD pin assignment (PSDPAR) 26-21
port TC pin assignment (PTCPAR) 26-24
port TD pin assignment (PTDPAR) 26-25
port UA pin assignment (PUAPAR) 26-26
digital input 26-28
digital output 26-28
,
26-4
,
26-3
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
,
20-11
I
I
IDCODE instruction 31-7
Identifier (ID) bits 25-7
IDLE bit 25-27
Information processing time (IPT) 25-13
Input capture 20-17
Instructions
Intermission 25-12
Interrupt controller
2
C
arbitration procedure 24-11
clock
electrical characteristics
handshaking 24-12
memory map 24-3
operation 24-7
programming examples
registers
slave mode 24-14
timing diagrams
additions 2-14
execution timing
JTAG
RTE 2-21
arbitration 24-11
stretching 24-12
synchronization 24-11
input timing between SCL and SDA 33-20
output timing between SCL and SDA 33-20
low-power modes 7-8
initialization 24-12
repeated START generation 24-14
START generation 24-12
STOP generation 24-13
address (I2ADR) 24-3
control (I2CR) 24-4
data I/O (I2DR) 24-6
frequency divider (I2FDR) 24-3
status (I2SR) 24-5
input/output timing 33-21
miscellaneous 2-30
one-operand 2-28
two-operand 2-28
BYPASS 31-9
CLAMP 31-9
ENABLE_TEST_CTRL 31-8
EXTEST 31-7
HIGHZ 31-8
IDCODE 31-7
LOCKOUT_RECOVERY 31-8
SAMPLE/PRELOAD 31-7
TEST_LEAKAGE 31-8
Freescale Semiconductor
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