HD64F7145F50 Renesas Electronics America, HD64F7145F50 Datasheet - Page 13
![IC SUPERH MCU FLASH 256K FP144F](/photos/12/42/124218/hd64f7145f50_sml.jpg)
HD64F7145F50
Manufacturer Part Number
HD64F7145F50
Description
IC SUPERH MCU FLASH 256K FP144F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet
1.HD64F7144F50V.pdf
(932 pages)
Specifications of HD64F7145F50
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7145F50
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
HD64F7145F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F7145F50V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 6 Interrupt Controller (INTC) .............................................................. 77
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Section 7 User Break Controller (UBC) ........................................................... 101
7.1
7.2
7.3
7.4
Features .............................................................................................................................77
Input/Output Pins ..............................................................................................................79
Register Descriptions ........................................................................................................79
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources ...............................................................................................................87
6.4.1
6.4.2
6.4.3
6.4.4
Interrupt Exception Processing Vectors Table ..................................................................90
Operation...........................................................................................................................93
6.6.1
6.6.2
Interrupt Response Time ...................................................................................................96
Data Transfer with Interrupt Request Signals ...................................................................98
6.8.1
6.8.2
6.8.3
6.8.4
Features .............................................................................................................................101
Register Descriptions ........................................................................................................103
7.2.1
7.2.2
7.2.3
7.2.4
Operation...........................................................................................................................106
7.3.1
7.3.2
7.3.3
Examples of Use ...............................................................................................................109
Interrupt Control Register 1 (ICR1).....................................................................80
Interrupt Control Register 2 (ICR2).....................................................................82
IRQ Status Register (ISR)....................................................................................84
Interrupt Priority Registers A to J (IPRA to IPRJ)...............................................85
External Interrupts ...............................................................................................87
On-Chip Peripheral Module Interrupts ................................................................88
User Break Interrupt ............................................................................................88
H-UDI Interrupt ...................................................................................................89
Interrupt Sequence ...............................................................................................93
Stack after Interrupt Exception Processing ..........................................................95
Handling Interrupt Request Signals as Sources for DTC Activating and
CPU Interrupt, but Not DMAC Activating ..........................................................99
Handling Interrupt Request Signals as Sources for Activating DMAC,
but Not CPU Interrupt and DTC Activating ........................................................99
Handling Interrupt Request Signals as Source for DTC Activating,
but Not CPU Interrupt and DMAC Activating ....................................................99
Handling Interrupt Request Signals as Source for CPU Interrupt
but Not DMAC and DTC Activating ...................................................................100
User Break Address Register (UBAR) ................................................................103
User Break Address Mask Register (UBAMR) ...................................................103
User Break Bus Cycle Register (UBBR) .............................................................104
User Break Control Register (UBCR)..................................................................105
Flow of User Break Operation .............................................................................106
Break on On-Chip Memory Instruction Fetch Cycle ...........................................108
Program Counter (PC) Values Saved...................................................................108
Rev.4.00 Mar. 27, 2008, Page xi of xliv
REJ09B0108-0400
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