MCF5282CVM66J Freescale Semiconductor, MCF5282CVM66J Datasheet - Page 60

• Manufacturer Part Number: MCF5282CVM66J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ColdFire Core
2.3.2
The original ColdFire Instruction Set Architecture (ISA_A) was derived from the M68000 family opcodes
based on extensive analysis of embedded application code. The ISA was optimized for code compiled
from high-level languages where the dominant operand size was the 32-bit integer declaration. This
approach minimized processor complexity and cost, while providing excellent performance for compiled
applications.
After the initial ColdFire compilers were created, developers noted there were certain ISA additions that
would enhance code density and overall performance. Additionally, as users implemented ColdFire-based
designs into a wide range of embedded systems, they found certain frequently-used instruction sequences
that could be improved by the creation of additional instructions.
The original ISA definition minimized support for instructions referencing byte- and word-sized operands.
Full support for the move byte and move word instructions was provided, but the only other opcodes
supporting these data types are CLR (clear) and TST (test). A set of instruction enhancements has been
implemented in subsequent ISA revisions, ISA_B and ISA_C. The new opcodes primarily addressed three
areas:
2-14
1. Enhanced support for byte and word-sized operands
2. Enhanced support for position-independent code
3. Miscellaneous instruction additions to address new functionality
Register-to-Memory
Register-to-Register
Embedded-Load
Instruction Set Architecture (ISA_A+)
OEP.AGEX
OEP.AGEX
OEP.AGEX
OEP.DSOC
OEP.DSOC
OEP.DSOC
Core clock
Core Bus
Core Bus
Core Bus
(Store)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 2-15. V2 OEP Pipeline Execution Templates
DSOC
OC
DS
AGEX
next
next
EX
AG
op read
op write
OC
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