R5F61668MZN50FPV Renesas Electronics America, R5F61668MZN50FPV Datasheet - Page 1047
R5F61668MZN50FPV
Manufacturer Part Number
R5F61668MZN50FPV
Description
MCU FLASH 1024K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R5F61668MZN50FPV.pdf
(1416 pages)
Specifications of R5F61668MZN50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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21.4.4
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs
the receive clock pulse and returns an acknowledge signal. Figures 21.9 and 21.10 show the
operation timings in slave transmit mode. The transmission procedure and operations in slave
transmit mode are described below.
1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the
2. When the slave address matches in the first frame following the detection of the start
3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to
4. Clear TRS for end processing, and read ICDRR (dummy read) to release SCL.
5. Clear TDRE.
(Master output)
(Master output)
(Slave output)
WAIT in ICMR and CKS3 to CKS0 in ICCRA(initial setting). Set the MST and TRS bits in
ICCRA to select slave receive mode, and wait until the slave address matches.
condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the
rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA
and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically.
The continuous transmission is performed by writing the transmit data to ICDRT every time
TDRE is set.
1, with TDRE = 1. When TEND is set, clear TEND.
processing
ICDRR
ICDRS
RDRF
RCVD
User
SDA
SDA
SCL
Slave Transmit Operation
Data n-1
[5] Set RCVD then read ICDRR
Figure 21.8 Master Receive Mode Operation Timing 2
A
9
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
[6] Issue stop condition [7] Read ICDRR and clear RCVD
4
Bit 3
5
Bit 2
6
Rev. 1.00 Jan. 29, 2010 Page 1015 of 1380
Bit 1
7
Section 21 I
Data n
Bit 0
8
A/A
9
[8] Set slave receive mode
2
Data n
C Bus Interface 2 (IIC2)
REJ09B0596-0100
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