DF2372VFQ34V Renesas Electronics America, DF2372VFQ34V Datasheet - Page 431

• Manufacturer Part Number: DF2372VFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372VFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
Normal Transfer Mode:
Bit
31
to
24
23
to
0
Bit Name
—
EXDMA Transfer Count Register (EDTCR)
Initial Value
All 0
All 0
R/W
—
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of transfers,
and the transfer counter function is halted. In this
case, there is no transfer end interrupt by the
transfer counter. Setting H'FFFFFF specifies the
maximum number of transfers, that is 16,777,215.
During EXDMA transfer, this counter shows the
remaining number of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.
Rev.7.00 Mar. 18, 2009 page 363 of 1136
Section 8 EXDMA Controller (EXDMAC)
REJ09B0109-0700