DF36034GHJ Renesas Electronics America, DF36034GHJ Datasheet - Page 96
DF36034GHJ
Manufacturer Part Number
DF36034GHJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-Q
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GHJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GHJ
HD64F36034GHJ
HD64F36034GHJ
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Section 3 Exception Handling
3.4.3
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Rev. 4.00 Mar. 15, 2006 Page 62 of 556
REJ09B0026-0400
signal is sent to the interrupt controller.
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Interrupt Handling Sequence
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