HD64F2218UTF24 Renesas Electronics America, HD64F2218UTF24 Datasheet - Page 247
![IC H8S MCU FLASH 128K 100-TQFP](/photos/12/40/124067/hd64f2218utf24_sml.jpg)
HD64F2218UTF24
Manufacturer Part Number
HD64F2218UTF24
Description
IC H8S MCU FLASH 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Specifications of HD64F2218UTF24
Core Processor
H8S/2000
Core Size
16-Bit
Speed
24MHz
Connectivity
SCI, SmartCard, USB
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
For Use With
3DK2218-SS - KIT DEV H8S/2218 WINDOWS SIDESHW
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2218UTF24V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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2.2.64
STMAC (STore from MAC register)
Operation
MACH
or
MACL
Assembly-Language Format
STMAC MAC register, ERd
Operand Size
Longword
Description
This instruction moves the contents of a multiply-accumulate register (MACH or MACL) to a
general register. If the transfer is from MACH, the upper 22 bits transferred to the general register
are a sign extension.
This instruction is supported by the H8S/2600 CPU only.
Available Registers
ERd: ER0 to ER7
STMAC
ERd
ERd
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if a MAC instruction resulted in a
Z: Set to 1 if a MAC instruction resulted in a
V: Set to 1 if a MAC instruction resulted in
C: Previous value remains unchanged.
Note: * Execution of this instruction copies the N, Z,
negative MAC register value; otherwise
cleared to 0.
zero MAC register value; otherwise
cleared to 0.
an overflow; otherwise cleared to 0.
Rev. 4.00 Feb 24, 2006 page 231 of 322
—
I
and V flag values from the multiplier to the
condition-code register (CCR). If the STMAC
instruction is executed after a CLRMAC or
LDMAC instruction with no intervening MAC
instruction, the V flag will be 0 and the N and Z
flags will have undetermined values.
UI H
—
Section 2 Instruction Descriptions
Store Data from MAC Register
—
—
U
N
*
REJ09B0139-0400
Z
*
V
*
—
C
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