MC68HC11E0MFNE2 Freescale Semiconductor, MC68HC11E0MFNE2 Datasheet - Page 165
MC68HC11E0MFNE2
Manufacturer Part Number
MC68HC11E0MFNE2
Description
MCU 8-BIT 512 RAM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11E0MFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
52PLCC
Family Name
HC11
Maximum Speed
2 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC11E0MFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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PORT C (OUT)
Notes:
PORT C (OUT)
NOTES:
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (IN)
STRA (IN)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
Notes:
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
PORT C (OUT)
NOTES:
Figure 10-13. 3-State Variation of Output Handshake Timing Diagram
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRB (OUT)
1. After reading PIOC with STAF set
2. Figure shows rising edge STRA (EGA = 1) and high true STRB (INVB = 1).
STRA (IN)
STRA (IN)
E
(DDR = 1)
STRA (IN)
(DDR = 0)
STRA (IN)
(DDR = 0)
E
DDR = 1
DDR = 0
DDR = 0
PREVIOUS PORT DATA
PREVIOUS PORT DATA
Figure 10-12. Port C Output Handshake Timing Diagram
E
E
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
b) STRA ACTIVE AFTER PORTCL WRITE
a) STRA ACTIVE BEFORE PORTCL WRITE
WRITE PORTCL
READ PORTCL
WRITE PORTCL
READ PORTCL
OLD DATA
t
t
OLD DATA
PCD
PCD
M68HC11E Family Data Sheet, Rev. 5.1
(STRA Enables Output Buffer)
t
(1)
t
1
PWD
t
PWD
(1)
1
t
PWD
PWD
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
NEW DATA VALID
NEW DATA VALID
t
t
DEB
DEB
t
t
PCD
PCD
"READY"
“READY”
NEW DATA VALID
t
t
AES
AES
NEW DATA VALID
“READY”
"READY"
MC68L11E9/E20 Peripheral Port Timing
t
t
t
t
t
PCH
PCH
PCH
PCH
PCH
t
t
DEB
t
DEB
t
t
AES
t
t
t
AES
PCZ
PCZ
PCZ
PCZ
PORT C OUTPUT HNDSHK TIM
t
t
DEB
DEB
165
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