MC68CK16Z1CAG16 Freescale Semiconductor, MC68CK16Z1CAG16 Datasheet - Page 153

• Manufacturer Part Number: MC68CK16Z1CAG16
• Description: IC MICROPROCESSOR 16BIT 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68CK16Z1CAG16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 11
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 144LQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

5.6.6.1 Show Cycles
M68HC16 Z SERIES
USER’S MANUAL
The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS is not asserted exter-
nally during show cycles.
Show cycles are controlled by the SHEN[1:0] in SIMCR. This field is set to %00 by re-
set. When show cycles are disabled, the address bus, function codes, size, and read/
write signals reflect internal bus activity, but AS and DS are not asserted externally and
external data bus pins are in high-impedance state during internal accesses. Refer to
5.2.3 Show Internal Cycles
information.
When show cycles are enabled, DS is asserted externally during internal cycles, and
internal data is driven out on the external data bus. Because internal cycles normally
continue to run when the external bus is granted, one SHEN[1:0] encoding halts inter-
nal bus activity while there is an external master.
SIZ[1:0] signals reflect bus allocation during show cycles. Only the appropriate portion
of the data bus is valid during the cycle. During a byte write to an internal address, the
portion of the bus that represents the byte that is not written reflects internal bus con-
ditions, and is indeterminate. During a byte write to an external address, the data mul-
tiplexer in the SIM causes the value of the byte that is written to be driven out on both
bytes of the data bus.
RE-ARBITRATE OR RESUME PROCESSOR
1) ASSERT BUS GRANT (BG)
1) NEGATE BG (AND WAIT FOR
Figure 5-17 Bus Arbitration Flowchart for Single Request
BGACK TO BE NEGATED)
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
OPERATION
Freescale Semiconductor, Inc.
MCU
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
and the SIM Reference Manual (SIMRM/AD) for more
1) PERFORM DATA TRANSFERS (READ AND
1) NEGATE BGACK
1) ASSERT BUS REQUEST (BR)
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
WRITE CYCLES) ACCORDING TO THE SAME
RULES THE PROCESSOR USES
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
BUS ARB FLOW
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