MCF52255CAF80 Freescale Semiconductor, MCF52255CAF80 Datasheet - Page 27
![MCU 32BIT COLDFIRE V2 100LQFP](/photos/12/39/123950/mcf52255caf80_sml.jpg)
MCF52255CAF80
Manufacturer Part Number
MCF52255CAF80
Description
MCU 32BIT COLDFIRE V2 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5225xr
Datasheet
1.MCF52256CAG66.pdf
(46 pages)
Specifications of MCF52255CAF80
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF522x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
QSPI, I2C, UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
56
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
TWR-MCF5225X, TWR-SENSOR-PAK, TWR-SER, TWR-ELEV, TOWER, M52259EVB, M52259DEMOKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Electrical Characteristics
27
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9
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recommends the use of
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
recommends the use of
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
in conformance with Psi-JT.
recommends the use of
temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures
can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature
specification can be verified by physical measurement in the customer’s system using the
dissipation, and the method described in EIA/JESD Standard 51-2.
Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
Per JEDEC JESD51-6 with the board JESD51-7) horizontal.
100 LQFP
JA
JA
JA
and
and
and
jt
jt
jt
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale
Junction to ambient, natural convection
Junction to ambient, natural convection
Junction to ambient, (@200 ft/min)
Junction to ambient, (@200 ft/min)
Junction to board
Junction to case
Junction to top of package
Maximum operating junction temperature
JA
JA
JA
and power dissipation specifications in the system design to prevent device junction
and power dissipation specifications in the system design to prevent device junction
and power dissipation specifications in the system design to prevent device junction
Table 8. Thermal Characteristics (continued)
MCF52259 ColdFire Microcontroller, Rev. 4
Characteristic
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural convection
—
—
—
Symbol
JMA
JMA
T
JA
JA
JB
JC
jt
jt
jt
jt
j
parameter, the device power
parameter, the device power
parameter, the device power
Freescale Semiconductor
53
39
Value
42
33
25
105
9
2
13,14
1,15
17
18
1,3
1,3
16
C / W
C / W
C / W
C / W
C / W
C / W
C / W
Unit
o
C