MC908AP64ACBE Freescale Semiconductor, MC908AP64ACBE Datasheet - Page 199
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MC908AP64ACBE
Manufacturer Part Number
MC908AP64ACBE
Description
IC MCU 64K FLASH 8MHZ 42-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP64ACBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
30
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Controller Family/series
HC08
No. Of I/o's
30
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (2Mb)
12.9.4 IRSCI Status Register 1
SCI status register 1 contains flags to signal these conditions:
SCTE — SCI Transmitter Empty Bit
TC — Transmission Complete Bit
SCRF — SCI Receiver Full Bit
IDLE — Receiver Idle Bit
Freescale Semiconductor
•
•
•
•
•
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This clearable, read-only bit is set when the IRSCDR transfers a character to the transmit shift register.
SCTE can generate an SCI transmitter CPU interrupt request. When the SCTIE bit in IRSCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by
reading IRSCS1 with SCTE set and then writing to IRSCDR. Reset sets the SCTE bit.
This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being
transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in IRSCC2 is also
set. TC is automatically cleared when data, preamble or break is queued and ready to be sent. There
may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the
transmission actually starting. Reset sets the TC bit.
This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data
register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in IRSCC2
is set, SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading
IRSCS1 with SCRF set and then reading the IRSCDR. Reset clears SCRF.
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input.
IDLE generates an SCI receiver CPU interrupt request if the ILIE bit in IRSCC2 is also set. Clear the
IDLE bit by reading IRSCS1 with IDLE set and then reading the IRSCDR. After the receiver is enabled,
1 = IRSCDR data transferred to transmit shift register
0 = IRSCDR data not transferred to transmit shift register
1 = No transmission in progress
0 = Transmission in progress
1 = Received data available in IRSCDR
0 = Data not available in IRSCDR
Transfer of IRSCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to IRSCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
Parity error
Address:
Reset:
Read:
Write:
$0043
SCTE
Bit 7
1
Figure 12-15. IRSCI Status Register 1 (IRSCS1)
= Unimplemented
MC68HC908AP A-Family Data Sheet, Rev. 3
TC
6
1
SCRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
Bit 0
PE
0
I/O Registers
199
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