MC908GZ48CFAE Freescale Semiconductor, MC908GZ48CFAE Datasheet - Page 84
![IC MCU 48K FLASH 8MHZ 48-LQFP](/photos/12/38/123851/mc908gz48cfae_sml.jpg)
MC908GZ48CFAE
Manufacturer Part Number
MC908GZ48CFAE
Description
IC MCU 48K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GZ60CFJE.pdf
(352 pages)
Specifications of MC908GZ48CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Part Number:
MC908GZ48CFAE
Manufacturer:
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Manufacturer:
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Clock Generator Module (CGM)
PLLON — PLL On Bit
BCS — Base Clock Select Bit
VPR1 and VPR0 — VCO Power-of-Two Range Select Bits
84
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See
Selector
These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction
with L controls the hardware center-of-range frequency, f
PLLON bit is set. Reset clears these bits. (See
4.5.5 PLL VCO Range Select
1 = PLL on
0 = PLL off
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
Circuit.) Reset clears the BCS bit.
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0),
selecting CGMVCLK requires two writes to the PLL control register. (See
4.3.8 Base Clock Selector
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are
appropriate for the given reference and VCO clock frequencies before
enabling the PLL. See
on selecting the proper value for these control bits.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
1. Do not program E to a value of 3.
VPR1 and VPR0
Table 4-4. VPR1 and VPR0 Programming
00
01
10
Register.)
4.3.6 Programming the PLL
Circuit.).
2
NOTE
NOTE
NOTE
E
0
1
(1)
4.3.3 PLL
VRS
Circuits,
VCO Power-of-Two
Range Multiplier
. VPR1:VPR0 cannot be written when the
for detailed instructions
1
2
4
4.3.6 Programming the
4.3.8 Base Clock Selector
Freescale Semiconductor
4.3.8 Base Clock
PLL, and
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