MCF5328CVM240J Freescale Semiconductor, MCF5328CVM240J Datasheet - Page 34
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MCF5328CVM240J
Manufacturer Part Number
MCF5328CVM240J
Description
IC MPU RISC 240MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF532xr
Datasheet
1.MCF5328CVM240J.pdf
(50 pages)
Specifications of MCF5328CVM240J
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
Peripherals
DMA, LCD, PWM, WDT
Number Of I /o
94
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Family Name
MPC5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
240MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.6/1.95/2.75/3.6V
Operating Supply Voltage (min)
1.4/1.7/2.25/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
MA-BGA
Processor Series
MCF532xx
Core
ColdFire V3
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5328CVM240J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Electrical Characteristics
34
1
1
2
3
Num
S11
S12
S13
S14
S15
S16
S17
S18
All timings specified with a capactive load of 25pF.
Num
S10
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock
(SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the
minimum divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure
that SSI_BCLK does not exceed 4 x f
S6
S7
S8
S9
SSI_BCLK pulse width high/low
SSI_FS input setup before SSI_BCLK
SSI_FS input hold after SSI_BCLK
SSI_BCLK to SSI_TXD/SSI_FS output invalid/high
impedence
SSI_RXD hold after SSI_BCLK
SSI_BCLK cycle time
SSI_BCLK to SSI_TXD/SSI_FS output valid
SSI_RXD setup before SSI_BCLK
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
SSI_RXD / SSI_FS input hold after SSI_BCLK
Table 19. SSI Timing – Master Modes
MCF532x ColdFire
Description
Description
Table 20. SSI Timing – Slave Modes
SYS
.
®
Microprocessor Data Sheet, Rev. 5
Symbol
Symbol
1
t
BCLK
(continued)
1
8 × t
Min
45%
15
—
Min
-2
-4
0
10
10
—
-2
3
3
SYS
Max
—
15
—
—
Max
55%
—
15
—
—
—
—
—
—
Freescale Semiconductor
Units
Units
t
ns
ns
ns
ns
ns
BCLK
ns
ns
ns
ns
ns
ns
ns