MC9S12XEQ384MAG Freescale Semiconductor, MC9S12XEQ384MAG Datasheet - Page 967

• Manufacturer Part Number: MC9S12XEQ384MAG
• Description: MCU 16BIT 384K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ384MAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 24 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Package: 144LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
Freescale Semiconductor
FDIV[6:0]
FDIVLD
Address
Offset Module Base + 0x0000
Reset
& Name
Field
6–0
7
W
R
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written since the last reset
Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash
clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program
and erase algorithms.
Please refer to
Flash Clock Divider Register (FCLKDIV)
0
7
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
= Unimplemented or Reserved
7
Section 26.4.1, “Flash Command Operations,”
Figure 26-4. FTM384K2 Register Summary (continued)
0
6
Figure 26-5. Flash Clock Divider Register (FCLKDIV)
= Unimplemented or Reserved
Table 26-9
MC9S12XE-Family Reference Manual , Rev. 1.23
6
Table 26-8. FCLKDIV Field Descriptions
0
5
shows recommended values for FDIV[6:0] based on OSCCLK frequency.
5
CAUTION
0
4
Description
4
FDIV[6:0]
Chapter 26 384 KByte Flash Module (S12XFTM384K2V1)
0
3
for more information.
3
0
2
2
0
1
1
0
0
0
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