MCF5270VM100J Freescale Semiconductor, MCF5270VM100J Datasheet - Page 292

• Manufacturer Part Number: MCF5270VM100J
• Description: IC MCU 166MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5270VM100J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 61
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Chip Select Module
16.2.3 Byte Strobes (BS[3:0])
These signals are individually programmed through the byte-enable mode bit, CSCRn[BEM],
described in
These generated signals provide byte data select signals, which are decoded from the transfer size,
A1, and A0 signals in addition to the programmed port size and burstability of the memory
accessed, as shown below.
The below table also shows the interaction of the byte-enable/byte-write enables with related
signals.
16-2
Transfer Size
Longword
Section 16.4.1.3, “Chip Select Control Registers
Word
Byte
Table 16-1. Byte Enables/Byte Write Enable Signal Settings
Port Size
16-bit
32-bit
16-bit
32-bit
16-bit
32-bit
8-bit
8-bit
8-bit
MCF5271 Reference Manual, Rev. 2
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
D[31:24]
BS3
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
D[23:16]
BS2
1
1
1
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
(CSCR0–CSCR7).”
D[15:8]
BS1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
Freescale Semiconductor
D[7:0]
BS0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0