R5F2L388BNFA#U1 Renesas Electronics America, R5F2L388BNFA#U1 Datasheet - Page 240

• Manufacturer Part Number: R5F2L388BNFA#U1
• Description: MCU FLASH 64KB ROM 80LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/38Br

Specifications of R5F2L388BNFA#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 68
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 203 of 802
15.2.8
Note:
1. The results of writing to these bits are as follows:
NMIF Bit (Non-Maskable Interrupt Generation Bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0080h
• The bit is set to 0 when it is first read as 1 and then 0 is written to it.
• The bit remains unchanged even if it is first read as 0 and then 0 is written to it because its previous value is
• The bit’s value remains unchanged if 1 is written to it.
The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog
timer or oscillation stop detection) is generated.
The NMIF bit is set to 1 when a watchdog timer interrupt or an oscillation stop detection interrupt is generated.
When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is
generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed.
When an interrupt source is the watchdog timer, wait for the following cycles before writing 0 to the NMIF bit:
If the WDTC7 bit in the WDTC register is set to 0 (divide-by-16 using the prescaler), wait for 16 cycles of the
CPU clock after the interrupt source is generated.
If the WDTC7 bit is set to 1 (divide-by-128 using the prescaler), wait for 128 cycles of the CPU clock after the
interrupt source is generated.
When an interrupt source is oscillation stop detection, set to the OCD1 bit in the OCD register to 0 (oscillation
stop detection interrupt disabled) before writing 0 to the NMIF bit.
Symbol
retained. (The bit’s value remains 1 even if it is set to 1 from 0 after being read as 0 and having 0 written to it
because its previous value is retained.)
Symbol
Bit
NMIF
DTC Activation Control Register (DTCTL)
—
—
—
—
—
—
—
b7
—
0
Reserved bit
Non-maskable interrupt generation
bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
(1)
b6
—
0
Oct 30, 2009
Bit Name
b5
—
0
b4
—
0
Set to 0.
0: Non-maskable interrupts not generated
1: Non-maskable interrupts generated
b3
—
0
b2
—
0
Function
NMIF
b1
0
b0
—
0
15. DTC
R/W
R/W
R/W
—