M30262F4GP#U7 Renesas Electronics America, M30262F4GP#U7 Datasheet - Page 199
M30262F4GP#U7
Manufacturer Part Number
M30262F4GP#U7
Description
IC M16C/26 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Datasheets
1.M30622SAFPU5.pdf
(308 pages)
2.M30262F4GPU3.pdf
(41 pages)
3.M30262F4GPU3.pdf
(241 pages)
Specifications of M30262F4GP#U7
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
38
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
M30262F4GP#U7M30262F4GP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F4GP#U7M30262F4GP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30262F4GP#U7M30262F4GP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Preliminary Specifications Rev. 0.9
Specifications in this manual are tentative and subject to change.
M16C/26 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash memory control register 1 (FMR1):
Bit 1 allows the user to enter EW1 mode. This bit is relevant only if bit FMR01 is set.
Bit 7, when set to "0", inserts one wait state per access to Block A or B - regardless of the value of
PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled
by PM17 - regardless of the setting of FMR17. In cases where E/W cycles to Block A or B exceed 100
times (D7, D9, U7, U9), please set FMR17 to "1" (with wait).
Flash memory control register 4 (FMR4):
Bit 0 must be set to enable the erase-suspend feature.
Bit 1 is to be used to request a suspend of an erase operation. This bit is set automatically in EW1 by
a maskable interrupt, and by software in EW0. This bit is to be always cleared by software at the end
of the erase suspend.
Bit 6 indicates suspend status. Poll this bit in EW0 after requesting a suspend, before accessing the
flash.
191
Renesas Technology Corp.
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