R5F21274SNFP#U0 Renesas Electronics America, R5F21274SNFP#U0 Datasheet - Page 293
R5F21274SNFP#U0
Manufacturer Part Number
R5F21274SNFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21274SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21274SNFP#U0R5F21274SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
16.2.4
Table 16.4
NOTES:
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
Clock synchronous
communication mode
4-wire bus
communication mode
4-wire bus
(bidirectional)
communication mode
Communication Mode
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication
mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 16.4 shows the Association between Communication Modes and I/O Pins.
Sep 26, 2008
Communication Modes and Pin Functions
Association between Communication Modes and I/O Pins
(2)
Page 274 of 453
0
1
1
SSUMS
Disabled 0
0
1
BIDE
Bit Setting
1
0
1
0
1
MSS
0
1
0
1
0
1
0
1
0
1
0
1
TE
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
16. Clock Synchronous Serial Interface
RE
Input
−
Input
Input
−
Input
−
Output
Output
Input
−
Input
−
−
−
−
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SSI
Pin State
Output
Output
Output
−
Output
−
Output
Input
−
Input
−
Output
Input
Output
Input
Output
(1)
(1)
(1)
(1)
SSO
Input
Input
Input
Output
Output
Output
Input
Input
Input
Output
Output
Output
Input
Input
Output
Output
SSCK
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