M38039G6HSP#U0 Renesas Electronics America, M38039G6HSP#U0 Datasheet - Page 86

• Manufacturer Part Number: M38039G6HSP#U0
• Description: IC 740/3803 MCU QZROM 64DIP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039G6HSP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: QzROM
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H QzROM version)
REJ03B0166-0113 Rev.1.13
Page 84 of 100
2. Notes when selecting clock asynchronous serial I/O
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. S
When signals are output from the S
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the S
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/Oi (i = 1, 3) control register again
Set the serial I/Oi control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0.”
Fig 82. Sequence of setting serial I/Oi (i = 1, 3) control
5. Data transmission control with referring to transmit
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
S
transmit buffer register at “H” of the S
CLK
shift register completion flag
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set the bits 0 to 3 and bit 6 of the serial I/Oi
control register
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
RDY
i (i = 1, 3) input level. Also, write the transmit data to the
i (i = 1, 3) output of reception side
register again
RDY
CLK
Aug 21, 2009
i pin on the reception side
i input level.
RDY
Can be set with the
LDM instruction at
the same time
i output enable
7. Transmit interrupt request when transmit enable bit
When using the transmit interrupt, take the following sequence.
(1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to
(4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register shift completion flag are
also set to “1”.
Therefore, regardless of selecting which timing for the
generating of transmit interrupts, the interrupt request is
generated and the transmit interrupt request bit is set at this point.
8. Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the
transmission/reception operation is stopped.
Notes on PWM
The PWM starts from “H” level after the PWM enable bit is set
to enable and “L” level is temporarily output from the PWM pin.
The length of this “L” level output is as follows:
Notes on A/D Converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage
comparison. Accordingly, when signals from signal source with
high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion
precision to be worse.
2. A/D converter power source pin
The AV
using the A/D conversion function or not, connect it as following:
• AV
<Reason>
If the AV
because of noise or others.
2 × f(X
is set
“0” (disabled).
“0” after 1 or more instruction has executed.
“1” (enabled).
f(X
n + 1
n + 1
SS
: Connect to the V
SS
IN
SS
IN
)
pin is A/D converter power source pins. Regardless of
)
pin is opened, the microcomputer may have a failure
(s)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
SS
line
µ
F to 1
µ
F.