MC9S08AW48CFUE Freescale Semiconductor, MC9S08AW48CFUE Datasheet - Page 261
![IC MCU 48K FLASH 64-QFP](/photos/12/36/123634/mc9s08aw48cfue_sml.jpg)
MC9S08AW48CFUE
Manufacturer Part Number
MC9S08AW48CFUE
Description
IC MCU 48K FLASH 64-QFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08AW48CFUE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
64PQFP
Family Name
HCS08
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08AW48CFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S08AW48CFUER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 15
Development Support
15.1
Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
The alternate BDC clock source for MC9S08AW60 Series is the ICGLCLK. See
Chapter 8, “Internal
Clock Generator
(S08ICGV4)” for more information about ICGCLK and how to select clock sources.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
261
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