MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 408

• Manufacturer Part Number: MC9S08DZ128MLL
• Description: MCU 8BIT 128K FLASH 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128MLL

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Processor Series: S08DZ
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 88
• Number Of Timers: 3
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 87
• Eeprom Memory Size: 2KB
• Ram Memory Size: 8KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 18 Debug Module (S08DBGV3) (128K)
18.3.3.15 Debug Status Register (DBGS)
1
408
end-run
Module Base + 0x000E
end-run
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF, BF, and CF do not
change after reset.
Reset
ARMF
Field
POR
CF
AF
BF
7
6
5
0
W
R
1
Trigger A Match Bit — The AF bit indicates if Trigger A match condition was met since arming.
0 Comparator A did not match
1 Comparator A match
Trigger B Match Bit — The BF bit indicates if Trigger B match condition was met since arming.
0 Comparator B did not match
1 Comparator B match
Trigger C Match Bit — The CF bit indicates if Trigger C match condition was met since arming.
0 Comparator C did not match
1 Comparator C match
Arm Flag Bit — The ARMF bit indicates whether the debugger is waiting for trigger or waiting for the FIFO to fill.
While DBGEN = 1, this status bit is a read-only image of the ARM bit in DBGC. See
the DBG Module”
0 Debugger not armed
1 Debugger armed
AF
U
0
7
The DBG trigger register (DBGT) can not be changed unless ARM=0.
= Unimplemented or Reserved
BF
U
0
6
for more information.
Figure 18-16. Debug Status Register (DBGS)
TRG Value
Table 18-18. DBGS Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
Table 18-17. Trigger Mode Encoding
1001
1111
↓
CF
U
0
5
NOTE
0
0
0
4
Description
No Trigger
Meaning
0
0
0
3
0
0
0
2
Section 18.4.4.2, “Arming
Freescale Semiconductor
0
0
0
1
ARMF
1
0
0