MC908GZ32CFAE Freescale Semiconductor, MC908GZ32CFAE Datasheet - Page 249
![IC MCU 32K FLASH 8MHZ 48-LQFP](/photos/37/62/376278/tqfp-48_sml.jpg)
MC908GZ32CFAE
Manufacturer Part Number
MC908GZ32CFAE
Description
IC MCU 32K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GZ60CFJE.pdf
(352 pages)
Specifications of MC908GZ32CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
CAN/ESCI/SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
24-ch x 10-bit
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GZ32CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908GZ32CFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit.
SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
16.6.2 Mode Fault Error
Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the
MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins
as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of
the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
Freescale Semiconductor
•
•
The SS pin of a slave SPI goes high during a transmission
The SS pin of a master SPI goes low at any time
SPI RECEIVE
COMPLETE
Figure 16-11. Clearing SPRF When OVRF Interrupt Is Not Enabled
SPSCR
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
OVRF
READ
READ
SPDR
SPRF
1
2
3
4
5
6
7
BYTE 1
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
1
2
Figure 16-11
3
4
BYTE 2
5
illustrates this process. Generally, to avoid this second
BYTE 3
6
7
8
10
11
12
13
14
8
9
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
BYTE 4
10
11
12
13
14
Error Conditions
Figure
16-12.)
249
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