MC908AP32CFAER Freescale Semiconductor, MC908AP32CFAER Datasheet - Page 191

• Manufacturer Part Number: MC908AP32CFAER
• Description: IC MCU 32K FLASH 8MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AP32CFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, IRSCI, SCI, SPI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.5.3.2 Character Reception
During an SCI reception, the receive shift register shifts characters in from the RxD pin. The SCI data
register (IRSCDR) is the read-only buffer between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data portion of the character transfers
to the IRSCDR. The SCI receiver full bit, SCRF, in IRSCI status register 1 (IRSCS1) becomes set,
indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in IRSCC2 is
also set, the SCRF bit generates a receiver CPU interrupt request.
12.5.3.3 Data Sampling
The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency
16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at the following
times (see
To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three
logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.
Table 12-2
Freescale Semiconductor
•
•
RT CLOCK
RT CLOCK
SAMPLES
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit
samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
SCI_RxD
CLOCK
RESET
STATE
Figure
RT
summarizes the results of the start bit verification samples.
12-9):
RT3, RT5, and RT7
QUALIFICATION
START BIT
Figure 12-9. Receiver Data Sampling
MC68HC908AP Family Data Sheet, Rev. 4
Samples
Table 12-2. Start Bit Verification
000
001
010
VERIFICATION
START BIT
Verification
Start Bit
Yes
Yes
Yes
START BIT
SAMPLING
DATA
Noise Flag
0
1
1
SCI Functional Description
LSB
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