MC908AP16ACFAE Freescale Semiconductor, MC908AP16ACFAE Datasheet - Page 196
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MC908AP16ACFAE
Manufacturer Part Number
MC908AP16ACFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP16ACFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP16ACFAE
Manufacturer:
FREESCALE
Quantity:
9
Company:
Part Number:
MC908AP16ACFAE
Manufacturer:
Freescale Semiconductor
Quantity:
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Infrared Serial Communications Interface Module (IRSCI)
12.9.2 IRSCI Control Register 2
IRSCI control register 2:
SCTIE — SCI Transmit Interrupt Enable Bit
TCIE — Transmission Complete Interrupt Enable Bit
SCRIE — SCI Receive Interrupt Enable Bit
ILIE — Idle Line Interrupt Enable Bit
TE — Transmitter Enable Bit
196
•
•
•
•
•
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset
clears the SCTIE bit.
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
This read/write bit enables the SCRF bit to generate SCI receiver CPU interrupt requests. Reset clears
the SCRIE bit.
This read/write bit enables the IDLE bit to generate SCI receiver CPU interrupt requests. Reset clears
the ILIE bit.
Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the
transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any
transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting
TE during a transmission queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
1 = Transmitter enabled
0 = Transmitter disabled
Enables the following CPU interrupt requests:
–
–
–
–
Enables the transmitter
Enables the receiver
Enables SCI wakeup
Transmits SCI break characters
Enables the SCTE bit to generate transmitter CPU interrupt requests
Enables the TC bit to generate transmitter CPU interrupt requests
Enables the SCRF bit to generate receiver CPU interrupt requests
Enables the IDLE bit to generate receiver CPU interrupt requests
Address:
Reset:
Read:
Write:
SCTIE
$0041
Bit 7
0
Figure 12-13. IRSCI Control Register 2 (IRSCC2)
TCIE
MC68HC908AP A-Family Data Sheet, Rev. 3
6
0
SCRIE
5
0
ILIE
4
0
TE
3
0
RE
2
0
RWU
1
0
Freescale Semiconductor
Bit 0
SBK
0
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